using latches in design
latches are wondrous things, and are the solution to good designs, compact chips, and peace on earth. Three clear advantages of latches are:
1.Considerably smaller than D-type flip-flops
2.Provide anticipation of the data (for example, the decode of a latched address can begin before the latch is closed)
3.Lower power, compared with continuously clocked flip-flops.
If you do insist on a latch-based design, watch out for the following:
1.A glitch-free enable—remember that glitches on the enable can corrupt the latch’s data. If you are synthesizing the code to create the enable, consider seriously the direct instantiation of the gate that drives the enable to the latch. Don’t trust optimized equations!
2.Data input hold time—ensure that the data is held for long enough as you close the latch. If your latch enable is derived from a clock, the latch will lag the clock, requiring the latch’s D inputs to be held valid after the clock edge