arbalez
Member level 5
why modelsim is the most popular eda tool for practicing and designing using vhdl, verilog and systemc code?
is it because we must write our own testbenches to test our UUTs? unlike any other tool that has integrate testbench within its software?
is it because we must write our own testbenches to test our UUTs? unlike any other tool that has integrate testbench within its software?