[SOLVED] Why LVS is performed before STARRC

[beginner_1980]

Hi Guys,

I am a beginner and want to know why do we usually performs an LVS check before extraction ?
Can't we do RC extraction without LVS ? if No, why ?

 

[vijay.mani884]

alright, LVS is "Layout versus Schematic" I hope you understand that. fist of all its very important to understand what is what. So, supposing you have designed basic gates in schematic capture, then you will move on to layout correct? now think for a moment, how do you make sure that your schematic and layout are same? supposing if you have designed an inverter, where in you connect pmos in pull up and nmos in pull down, no considering the worst case, if while designing the layout if you connect nmos in pull up and pmos in pull down, then what will hap? (i know usually it never hap, i have given you a worst case example, there are other factors as well, like the device you choose while doing the schematic capture and while laying out the design.) so are they same? if your answer is NO! then what you should do? suposing you feel that huh!! it doesn't matter to me, and if you proceed to RC extraction, it will perform, but you wont get the desire result.

thats why it is LVS is must before you perform RC extractions. Rc extarctions provides the parasitic information of your design. If your design itself is not proper, then the parasitic information is of no use.

I hope it will help you to think further.


Cheers

 

[yadavvlsi]

If you have shorts and open in your design. It will effect your accuracy of parasitic extraction. But it is not necessary to perform LVS before extraction.

 

[jeevan.life]

If you have shorts and open in your design. It will effect your accuracy of parasitic extraction. But it is not necessary to perform LVS before extraction.

I agree with Yadav, but if you are doing your signoff runs, you have to perform LVS before extraction, else for dirty runs you can proceed for initial timing and stuff.

 

[GI]

Hi beginner_1980,

Whether you do LVS before extraction or not may depend on at which step you are, and on the number of problematic nets you have (e.g. shorts, opens).

For example if you have 500000 nets in a design, and you have 100 shorts, it may be ignorable while you're on timing (setup, hold) or design rule violation (max_transition, max_capacitance, ...) fixing loops. As the design converges, you'll definitely need to clean all shorts and opens, where you'll do a final extraction to be used in signoff quality timing analysis.

On the other hand, if you have 1000 nets in your design and you have 100 shorts your extraction may not be reliable and maybe most of your fixes are not needed.

I'm not an extraction expert but in my point of view, extraction tools should be smart enough to identify nets using their labels to extract correct resistance/capacitance on related net.

Best regards,
Gökhan
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[beginner_1980]

Thanks Vijay

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Thanks Vijay

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In fact, thanks to all...