alright, LVS is "Layout versus Schematic" I hope you understand that. fist of all its very important to understand what is what. So, supposing you have designed basic gates in schematic capture, then you will move on to layout correct? now think for a moment, how do you make sure that your schematic and layout are same? supposing if you have designed an inverter, where in you connect pmos in pull up and nmos in pull down, no considering the worst case, if while designing the layout if you connect nmos in pull up and pmos in pull down, then what will hap? (i know usually it never hap, i have given you a worst case example, there are other factors as well, like the device you choose while doing the schematic capture and while laying out the design.) so are they same? if your answer is NO! then what you should do? suposing you feel that huh!! it doesn't matter to me, and if you proceed to RC extraction, it will perform, but you wont get the desire result.
thats why it is LVS is must before you perform RC extractions. Rc extarctions provides the parasitic information of your design. If your design itself is not proper, then the parasitic information is of no use.
I hope it will help you to think further.
Cheers