light-doped region of drain below gate electrode>>
- parasitic capacitance is suppressed
- the intensity of electric field in drain is decreased
- suppressed the probability of formation of hot electrons
heavy doped drain region far away from gate electrode>>
- serial resistance of drain is suppressed
To others, you have only answered with standard answer from textbooks, that is LDD is used to reduce the electric field strength, the gate-drain capacitance and the hot electron impact ionisation effect.
If you are a device engineer, you will know that LDD is only used in NMOS only, not PMOS.
From device engineering view point, LDD reduces the drain-bulk depletion region at the reversed biased junction diode. Therefore LDD reduces leakage current through this diode. This is especially important in advanced nodes at ultra-DSM.