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Why is net delay becoming more prominent than cell delay in lower technologies

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limitless_21

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Hi ,

I wanted to know why net delay is dominating the cell delay in the lower technologies ?
The reasons can be - net length , net area, No. of vias traveresed by net or due to crosstalk, Also the net delay is the function of R & C values.
Apart from this what is the main factor still causing net delay to occur or if I frame my question again - on what all parameters does net delay depends apart from the above mentioned reasons)

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limitless
 

erikl

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Cell dimensions shrink quadratically with decreasing process size, so cell capacitances shrink at least stronger than linearly with decreasing process size (because of their mix of devices and interconnections). Interconnections' capacitances - in contrast - shrink very slowly - much less than linearly - with decreasing process size, s. e.g. these ITRC Interconnect Tables, table 2013_INTC2 for the years 2013-2028 (line 4) forecast. The pF/cm ( ≙ 0.1 fF/µm ) values (line 36 for M1, line 62 for intermediate, line 93 for global wires) decrease only insignificantly with decreasing process size (s. pitch resp. gate length, lines 5-7), keeping values between 0.2 and 0.1 fF/µm , during a process size shrink factor of about 4 .
 

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