library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity mac is
Port( in1 : in signed(11 downto 0);
in2 : in signed(11 downto 0);
clk : in std_logic;
rst : in std_logic;
acc : out signed(23 downto 0));
end mac;
architecture behavioural of mac is
signal prod, reg : signed(23 downto 0);
begin
process(clk,rst,in1,in2)
variable sum : signed(23 downto 0);
begin
prod <= in1 * in2;
if (rst'event and rst = '0') then
reg <= (OTHERS=>'0');
elsif (clk'event and clk='0') then
sum := prod + reg;
reg <= sum;
acc <= reg;
end if;
end process;
end behavioural;
...
if (rst'event and rst = '0') then
...
acc <= reg;
trurl said:Hi,
Can anybody tell why the following code can not be synthesized?
Xilinx says signal acc can not be synthesized.
Code:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity mac is Port( in1 : in signed(11 downto 0); in2 : in signed(11 downto 0); clk : in std_logic; rst : in std_logic; acc : out signed(23 downto 0)); end mac; architecture behavioural of mac is signal prod, reg : signed(23 downto 0); begin process(clk,rst,in1,in2) variable sum : signed(23 downto 0); begin prod <= in1 * in2; if (rst'event and rst = '0') then reg <= (OTHERS=>'0'); elsif (clk'event and clk='0') then sum := prod + reg; reg <= sum; acc <= reg; end if; end process; end behavioural;
Thanks in advance.
Regards.
if reset=0 then
blablabla
elsif rising_edge(clk) then
blablabla ..
endif
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity mac is
Port( in1 : in signed(11 downto 0);
in2 : in signed(11 downto 0);
clk : in std_logic;
rst : in std_logic;
acc : out signed(23 downto 0));
end mac;
architecture behavioural of mac is
signal prod, reg : signed(23 downto 0);
begin
prod <= in1 * in2;
acc <= reg;
process (clk,rst)
begin
if (rst = '0') then
reg <= (OTHERS=>'0');
elsif (clk'event and clk='0') then
reg <= prod + reg;
end if;
end process;
end behavioural;
nand_gates said:here is corrected code!
Code:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity mac is Port( in1 : in signed(11 downto 0); in2 : in signed(11 downto 0); clk : in std_logic; rst : in std_logic; acc : out signed(23 downto 0)); end mac; architecture behavioural of mac is signal prod, reg : signed(23 downto 0); begin prod <= in1 * in2; acc <= reg; process (clk,rst) begin if (rst = '0') then reg <= (OTHERS=>'0'); elsif (clk'event and clk='0') then reg <= prod + reg; end if; end process; end behavioural;
trurl said:To omara007:
Thank you. I added in1 and in2 to the sensitivity list, because Xilinx was giving warnings about them missing in the list.
trurl said:To omara007:
I have tried the code that you mentioned. The waves are wrong, the mac unit does not work properly.
The reason I use my (rst'event and rst= '0') statement is that I need to generate automatically reset pulse. Since my code is not synthesizable, may be you could advise how to generate a short rst pulse between 2 clk pulses periodically after some number of clk pulses. Thank you.
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