why is it not synthesizable?

[trurl]

Hi,

Can anybody tell why the following code can not be synthesized?

Xilinx says signal acc can not be synthesized.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity mac is
    Port( in1 : in  signed(11 downto 0);
            in2 : in  signed(11 downto 0);
            clk : in  std_logic;
            rst : in  std_logic;
            acc : out signed(23 downto 0));
end mac;

architecture behavioural of mac is
	signal prod, reg : signed(23 downto 0);
begin
	process(clk,rst,in1,in2)
		variable sum : signed(23 downto 0);
        begin
		prod <= in1 * in2;
                if (rst'event and rst = '0') then
		       reg <= (OTHERS=>'0');
		elsif (clk'event and clk='0') then
			sum := prod + reg;
		        reg <= sum;
			acc <= reg;
		end if;
	end process;
end behavioural;

Thanks in advance.

Regards.

 

[bis_]

Describe type of the Xilinx device is used. The following statement:

...
if (rst'event and rst = '0') then 
...

may be the problem. Edge triggered reset is rather not implementet in most of the Xilinx devices. Your design requires two, edge triggered inputs to the register (rst and clk). Try with async reset.

bis

 

[trurl]

Bis, thank you.

Since I'm a beginner, could you explain what is "async reset"
is it something like this
...
if (rst = '0') then
...

 

[wael_sharkasy]

Bring this line

acc <= reg;

under end if ( out of the if module) and try to synthesis again.
May be the problem that you have to assign the value of acc for both conditions.

 

[trurl]

I have tried it, it did not work in my experiment at least :-(

 

[omara007]

change all the (signed) signals , to (std_logic and std_logic_vector) signals .. and use the IEEE signed package in the begining of the file ..
Try to synthesize and feed me baq with what u get ..

 

[echo47]

I think bis_ is correct. Most flops, including Xilinx FPGA flops, don't have an edge-triggered reset input.

I changed your edge-triggered reset: if (rst'event and rst = '0') then
to an ordinary level-sensitive (asynchronous) reset: if (rst = '0') then
and now it synthesizes in ISE 9.1i.

 

[trurl]

To echo47:

I have already tried it, it synthesizes, but with this I get wrong waveforms in my design. Thanks anyway.

 

[omara007]

Hi,

Can anybody tell why the following code can not be synthesized?

Xilinx says signal acc can not be synthesized.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity mac is
    Port( in1 : in  signed(11 downto 0);
            in2 : in  signed(11 downto 0);
            clk : in  std_logic;
            rst : in  std_logic;
            acc : out signed(23 downto 0));
end mac;

architecture behavioural of mac is
	signal prod, reg : signed(23 downto 0);
begin
	process(clk,rst,in1,in2)
		variable sum : signed(23 downto 0);
        begin
		prod <= in1 * in2;
                if (rst'event and rst = '0') then
		       reg <= (OTHERS=>'0');
		elsif (clk'event and clk='0') then
			sum := prod + reg;
		        reg <= sum;
			acc <= reg;
		end if;
	end process;
end behavioural;

Thanks in advance.

Regards.

You have a problem in ur sensitivity list .. for the clocked processes, remove everythign from the sensitivity list except the clock and the reset ..
Also you shouldn't have 2 edge triggered signals in your design .. keep the clock edge triggered and make the reset asynchronous to it like this :

if reset=0 then
   blablabla
elsif rising_edge(clk) then
   blablabla ..
endif

 

[nand_gates]

here is corrected code!

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 

entity mac is 
    Port( in1 : in  signed(11 downto 0); 
          in2 : in  signed(11 downto 0); 
          clk : in  std_logic; 
          rst : in  std_logic; 
          acc : out signed(23 downto 0)); 
end mac;    

architecture behavioural of mac is 
   signal prod, reg : signed(23 downto 0); 
begin
  prod <= in1 * in2;
  acc <= reg; 
   process (clk,rst) 
   begin   
     if (rst = '0') then 
         reg <= (OTHERS=>'0'); 
     elsif (clk'event and clk='0') then 
       reg <= prod + reg; 
     end if; 
   end process; 
end behavioural;

 

[omara007]

here is corrected code!

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 

entity mac is 
    Port( in1 : in  signed(11 downto 0); 
          in2 : in  signed(11 downto 0); 
          clk : in  std_logic; 
          rst : in  std_logic; 
          acc : out signed(23 downto 0)); 
end mac;    

architecture behavioural of mac is 
   signal prod, reg : signed(23 downto 0); 
begin
  prod <= in1 * in2;
  acc <= reg; 
   process (clk,rst) 
   begin   
     if (rst = '0') then 
         reg <= (OTHERS=>'0'); 
     elsif (clk'event and clk='0') then 
       reg <= prod + reg; 
     end if; 
   end process; 
end behavioural;

True .. that's exactly what I have mentioned in the my previous message

 

[trurl]

To omara007:

Thank you. I added in1 and in2 to the sensitivity list, because Xilinx was giving warnings about them missing in the list.

 

[omara007]

To omara007:

Thank you. I added in1 and in2 to the sensitivity list, because Xilinx was giving warnings about them missing in the list.

ignore these warnings .. try removing these inputs ..

 

[vfdff]

if (rst'event and rst = '0') then
and
elsif (clk'event and clk='0') then
can't be used in one process !!

 

[omara007]

Please try the code nand_gates has posted and ignore any warning you get .. then tell us about the wave results

 

[trurl]

To vfdff:

Thanks. Why is that?

 

[Alfred_zhang]

I think Xilinx allways synthesize xx in statement "if (xx'event and xx = '0/1') " as a clk pin of the FlipFlop, there is only one clk pin in a FF cell. So there should not be two such statements in one process. One process one clock domain.

 

[trurl]

To omara007:

I have tried the code that you mentioned. The waves are wrong, the mac unit does not work properly.

The reason I use my (rst'event and rst= '0') statement is that I need to generate automatically reset pulse. Since my code is not synthesizable, may be you could advise how to generate a short rst pulse between 2 clk pulses periodically after some number of clk pulses. Thank you.

 

[omara007]

To omara007:

I have tried the code that you mentioned. The waves are wrong, the mac unit does not work properly.

The reason I use my (rst'event and rst= '0') statement is that I need to generate automatically reset pulse. Since my code is not synthesizable, may be you could advise how to generate a short rst pulse between 2 clk pulses periodically after some number of clk pulses. Thank you.

Try designing a simple counter (cnt) .. when this counter counts 2 clock cycles, assert a certain signal, let's call it (xyz) ..

You can use the combinational "when" statement to assign a value of '1' to the (xyz) when (cnt) counter is equal to (2) ..

After that you can use this signal in an "if" statement to force all other signals in the design to be ZERO .. but don't call it reset ..