Setup and hold are data:clock timing. If clock jitters
relative to data then you "could" see hold time as well
as setup time "noise". On the other hand almost every
FF design I've ever done or seen has finite setup but
"zero" (that is, less than zero, fuggedaboudit) hold time.
I guess my point there is that just because you don't
see, or aren't presented, a hold-time-jitter criterion
doesn't mean there is no effect. It may just mean the
hold time is -100pS +/- 10pS, rather than -100pS
period. So maybe 0 hold time buries either case and
it's one less constraint to bother the synthesis for
no upside.
When you're pushing the limits of a technology to
the point that you have to design clocked data paths
in Spectre / SPICE with layout parasitics, and up
against the FF+logic delay vs clock period per stage,
you will worry about clock jitter because setup time
is clock->data(clock)->clock. Same should be true of
hold, but you seldom run into hold time issues if there
is significant data delay from clock.