Why is 'ddiscrete' not allowed in verilog-AMS simulation?

`include "disciplines.vams"
module a2d(dnet1a, anet);
input dnet1a;
output anet;
wire dnet1a;
ddiscrete dnet1a;
electrical anet;
real avar;

analog begin
if (dnet1a === 1'b1)
avar = 5;
else if (dnet1a === 1'bx)
avar = avar; // hold value
else if (dnet1a === 1'b0)
avar = 0;
else if (dnet1a === 1'bz)
avar = 2.5; // high impedance - float value
V(anet) <+ avar;
end
endmodule

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ERROR: syntax error near discrete
C:\Users\rj\Documents\SMASH_Verilog_AMS_prj\one_bit_dac.vams(27): discrete dnet1a;

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discipline logic
domain discrete;
enddiscipline

discipline ddiscrete
domain discrete;
enddiscipline

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