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Why is 'ddiscrete' not allowed in verilog-AMS simulation?

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ruwan2

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Hi,

I see the below code from verilog-AMS reference book.




`include "disciplines.vams"
module a2d(dnet1a, anet);
input dnet1a;
output anet;
wire dnet1a;
ddiscrete dnet1a;
electrical anet;
real avar;

analog begin
if (dnet1a === 1'b1)
avar = 5;
else if (dnet1a === 1'bx)
avar = avar; // hold value
else if (dnet1a === 1'b0)
avar = 0;
else if (dnet1a === 1'bz)
avar = 2.5; // high impedance - float value
V(anet) <+ avar;
end
endmodule
When I run simulation of it in SMASH 6.3.0, it has error message:

ERROR: syntax error near discrete
C:\Users\rj\Documents\SMASH_Verilog_AMS_prj\one_bit_dac.vams(27): discrete dnet1a;
I have included `include "disciplines.vams". And that file has ddiscrete definition:

discipline logic
domain discrete;
enddiscipline

discipline ddiscrete
domain discrete;
enddiscipline

What is a solution for this? The AMS standard, or the EDA software?


Thanks,
 
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