not entirely sure. to be sure, there is no tri-port b-ram primitive in the spartan. but one can be made for the 1 write, 2 read case by using twice as much block ram. the write is the same for both sets of block ram, but the reads are independent.
Next, the spartan doens't have primitives with 12b inputs, but rather has 9b/18b/36b/72b inputs. thus some amount of space is wasted. coregen may be able to do a better job than the synthesis tool, and reduce the amount of wasted RAM.
i suspect the design uses 20k. 16k from needing the two reads, and the rest lost due to poor mapping to the actual block rams.
as before, look into converting this design into FIFOs or simple dual port block rams. One way to do this is to exploit the read pattern:
(0 1) (1 2) (2 3) (3 4) ...
could be converted to "read 0" "read 1 and store" "read 2 and use the stored 1" "read 3 and use the stored 2" ...
failing this, it might be possible to run the read clock at 2x (or faster). then you can read from two addresses in two clock cycles -- 1 per cycle.
also, you are using "write_enable" in both adc_clk and clk processes. ISE won't give you warnings about this, but this design practice will almost always fail eventually.
lastly, temp_sum is used without any obvious initialization or reset.