Why floatiss poly is used for a single transistor?

[VLSI_Learner]

Why for a single transistor two floatiss poly is placed?

For reference please see the picture

 

[dick_freebird]

There is not much detail here, so assumptions have to be
made. I'll assume your contact and S/D metal stripes lie
between the center poly and the endcap poly pieces.

In that case I'd say it's all about lithography, etch loading
and photoresist optics. To make a single, isolated stripe
match the geometry of multistripe devices (and that is a
goal, uniformity of outcomes) the close-in detail has to
match.

 

[VLSI_Learner]

You are right on your assumption.
But I didn't get the explanation. Please help.

 

[erikl]

But I didn't get the explanation. Please help.

First you should explain what you mean with floatiss - it's not a word known in English language.

Otherwise I think dick_freebird is right: the side poly stripes limit the S/D regions, providing a continuous environment for several active stripes in a row.

If you don't understand an explanation, you'd better tell what you don't understand - don't let us guess!

 

[VLSI_Learner]

Those poly at both ends serves as dummy poly only, of no use in circuit connectivity or device formation.
Here I am talking about a single transistor. When we say single transistor we mean one S/D region and one poly. But in 22nm technology when we place one single transistor we also get those two dummy transistors at both ends.
I heard that there was no such dummy transistors associated with a single transistors in 180nm technologies or other technology. Please explain.

 

[erikl]

Re: Why floating poly is used for a single transistor?

May be the dummy poly is used as shield (distance holder) against the proximity effect, see e.g. this thread.

If this (possible) explanation doesn't make you happy, I'd recommend to directly ask the 22nm tech. providers like amd, intel, tsmc.

 

[dick_freebird]

If you don't poly-mask the S/D ends then you are left
with implant photoresist tolerances, which are certain
to be looser and more variable than the critical poly mask.
Go look at your foundry CD specs and see how bad.

 

[VLSI_Learner]

There is not much detail here, so assumptions have to be
made. I'll assume your contact and S/D metal stripes lie
between the center poly and the endcap poly pieces.

In that case I'd say it's all about lithography, etch loading
and photoresist optics. To make a single, isolated stripe
match the geometry of multistripe devices (and that is a
goal, uniformity of outcomes) the close-in detail has to
match.

What is load etching and photo resist optics? And how lithography affects here?

If you don't poly-mask the S/D ends then you are left
with implant photoresist tolerances, which are certain
to be looser and more variable than the critical poly mask.
Go look at your foundry CD specs and see how bad.

What is implant photoresist tolerance?

 

[VLSI_Learner]

Please explain this.

 

[wizard of oz]

Latest techologies rely on optical interference to etch the photoresist for the gates. As such you have to have these dummy gates at the end to etch correctly the last gate.

 

[VLSI_Learner]

Can you please explain a little bit more?