why FIFO can attenuate jitter ?

[alchip]

For Tx & Rx design, we always add FIFO to decrease jitter.
Could you explain or show that ?

 

[Eugen_E]

It's not an analog question.
At the FIFO input, the data it's very bursty, but the reading it's done at a fixed rate.
So if u start inserting data without reading for a period, after a while some amount of data will be cached in the FIFO, no matter the input jitter.
If the reading it's done at a fixed rate, the output data will have no jitter, provided the FIFO it's not empty. The input data will keep the FIFO from getting empty, if the jitter it's not huge. So the output jitter will be much lower, because u see output jitter only when the FIFO it's empty.
To reduce very much the jitter, u need a long FIFO and to wait a fair amount of time to cache much data, so that input jitter would not affect much the FIFO level.

The FIFO size is a compromise - in real time applications you can't wait to much to cache data in FIFO and start to read sooner.