Because the board is designed so. Ask Xilinx.
I am not sure if there is FPGA IO connected to PHY chip clock pin, but I am pretty sure it is not, so You will not be able to wire the clock signal from FPGA until You won't do some soldering stuff to connect those pins. Anyway, DCM is a bit crap, since generates a lot of jitter, also there are RX/TX clock pins to do data sync, so learn how to use them. Having Your generated clock in the PHY would be OK, if there would be no delays inside the chip which could be a great PITA for correct design...