Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Why does SDF back annotate a wrong delay value on simulator?

Status
Not open for further replies.

Peter Chang

Junior Member level 2
Joined
Oct 5, 2006
Messages
21
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Location
TAIWAN
Activity points
1,419
Dear Sir,

I met one strange thing that the cell delay value is different from the delay value in SDF file, while doing a post simulation. From the log file, the sdf file has been read. And only
have some unimportant warnings. Why is the cell delay value in SDF different from what
I see on simulator? Thanks.


Peter:sad:
 

1- you backannotated the value with the correct (min:typ:max) from sdf?
2- negative value are change to zero in Questa simulator, for example.
 

Yes. The IOPATH DELAY is

(IOPATH A Y (0.487::0.487) (0.466::0.466))

But the value I saw is 0.213 ns and 0.167ns on simulator.

I used ncverilog to generate FSDB and verdi to check
the waveform.


Peter
 

So you backannotate wich the max or the min value, because the typical does not exist, right?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top