u24c02
Advanced Member level 1
Hi.
Now I'm trying to implement with RTM books about event control iff in system verilog.
For example,
why do we use this event control iff for what? It seems like clock gating. But I'm not sure.
I want to know practically usage not textbook.
I used to use like this.
What is the benefit a switch off of event trigger? May it can make an expression another way.
Now I'm trying to implement with RTM books about event control iff in system verilog.
For example,
always@( posedge clk iff rst=0 or posedge rst )
why do we use this event control iff for what? It seems like clock gating. But I'm not sure.
I want to know practically usage not textbook.
I used to use like this.
always@(posedge clk or negedge rst)
begin
if(!rst)
~~~~
else
~~~~
end
begin
if(!rst)
~~~~
else
~~~~
end
What is the benefit a switch off of event trigger? May it can make an expression another way.
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