why do we use event control iff in system verilog?

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Hi.

Now I'm trying to implement with RTM books about event control iff in system verilog.

For example,

always@( posedge clk iff rst=0 or posedge rst )​

why do we use this event control iff for what? It seems like clock gating. But I'm not sure.

I want to know practically usage not textbook.
I used to use like this.

always@(posedge clk or negedge rst)
begin
if(!rst)
~~~~
else
~~~~
end​

What is the benefit a switch off of event trigger? May it can make an expression another way.
 
Last edited:

Is this talking about synthesis or simulation. In simulation this may prevent processing the always block on a clock edge during reset - possibly saving some processor time.
In synthesis - yes - you would probably risk clock gating.
 

TrickyDicky said:
Is this talking about synthesis or simulation. In simulation this may prevent processing the always block on a clock edge during reset - possibly saving some processor time.
In synthesis - yes - you would probably risk clock gating.
Click to expand...

In simulation, practically, how much processor time reduced?
In synthesis, why do you think that why does it make a risk to clock gating?
 

Simulation processor time will depend on whats in the always block.
In Synthesis, it will have have to consider the signals in the timing control - it knows that events cannot occur on the clock edge when reset is high, so it will gate the clock with the reset. It may also synthesise it so that the reset becomes part of the synchronous enable. You may be at the mercy of the compiler.
 

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