why do we need frequency synthesizers since we can just divide the frequency using basic circuit such as divide-by-n logic circuit? why do we need pll circuit to design frequency synthesizers?
How do i define the loop bandwidth for a PLL ? Is there a standard way of doing that ?
Lets say i have to design a PLL whose tuning range is 6GHz, and the reference frequency is 100MHz.
What factors does loop bandwidth depend upon? The loop bandwidth is needed to further design the components of the filter, but how to decide a reasonable value of the loop bandwidth ?
We use frequency synthesizer to generate different clock signals with different frequencies and all are referenced to a stable (reference) oscialltor, which is almost a crystal.
From its name "Phase Locked Loops", i.e. when the loop locks the phase error between the output signal and the reference oscillator is constant or equal to zero, if Type I or Type II PLL respectively.
Added after 8 minutes:
haadi20 said:
How do i define the loop bandwidth for a PLL ? Is there a standard way of doing that ?
Lets say i have to design a PLL whose tuning range is 6GHz, and the reference frequency is 100MHz.
What factors does loop bandwidth depend upon? The loop bandwidth is needed to further design the components of the filter, but how to decide a reasonable value of the loop bandwidth ?
The loop bandwidth define many specs of the PLL, like the phase margin and the settling time and the phse noise levels and the spurs attenuation. So according to the application, which u r targeting, these specs is defined with the application standards.
For more information about the loop bandwidth and how to calculate it, try to read Nationa application note AN1001
Hello arbalez;
I think that we need frequency synthesizers and PLL circuits because of their precise and probably stable output frequency. This aspect is accessed by using feedback.
in the pll structure the phase noise from the VCO is greatly surpressed by the loop filter. The output frequency purity is greatly enhanced. Think of any open loop system and device parameter variation will cause big jitters in your frquency output.