Well the timing engine did not check if the paths are true. I means, the tool only sums the delay on the path between one flop to oneother flop, and the longest is the worst path, and as example if the same signal is connected to two AND gates of this path and require opposite value to allow the path to be active, the tools (include STA) do not check that.
STA has a additional option for the report_timing "-true_path", but the tool need to find a valid value for all inputs of all cells which involves in the path, that are very-very- time consumming.
For a design with 100kGate equivalent, Primetime was never able to return a path after 6hours of working.