Why data tran violation is present?

[kumaranurag21]

Hi

My timing is clean for my block but I still have data transition violation.Is it okay to say my design is closed or I need to fix all data tran violation?

 

[rca]

Re: Timing is clean yet data tran violation is there

no, your design could not really consider as clean.

The liberty timing table have two axis, one for the transition input and the second for the output load.
The warning indicate the transition is violated then the timing need to be extrapolated from the timing table, and then the value extrapolated could be pessimist or optimist. So dependant of the violation ratio, you could accepted this violation or need to fix it.
You could check, the path which contains this transition violation to check if the setup & hold have enough margin.

Also in some liberty, some pins have a max_transition smaller than the timing table have, then you need to check the real transition is always inside the table transition range and then you could waived this max transition violation.

 

[kumaranurag21]

Re: Timing is clean yet data tran violation is there

Thank you very much for the answer . One more query regarding clock tran violation.....do we always need to fix clock tran violation and if we not then what will be its impact on the design ??

 

[emiryu]

Re: Timing is clean yet data tran violation is there

Thank you very much for the answer . One more query regarding clock tran violation.....do we always need to fix clock tran violation and if we not then what will be its impact on the design ??

Clock path is in the same level with data path in the timing sign-off method, so it is...

 

[YuLongHuang]

Re: Timing is clean yet data tran violation is there

Typically, we need to fix "transition violation".
When you try to signoff, there is one design guideline provided by foundary.
There is one request for transition, maybe 1, maybe 0.5

 

[zjushmily]

Re: Timing is clean yet data tran violation is there

No. You'd better fix clock MTTV and Data MTTV first.
If there are big transition exist, delay calculation will not accurate, so you said "timing is clean" is a "false path"

 

[sameer_dlh25]

Re: Timing is clean yet data tran violation is there

My opinion need to fix all clock and data path.
One point is if transition is very close to lib range say max trans on data cell inside lib is 1 ns and you are at 1050 ps. In this case if timing path is met with decent margin [say 1 ns ] then probably you can wave it.
But it is hard to meet above criterion for too many paths so easier would be fixing these.
Just curious to know what prevent you to fix these, is it area or something else ?


Cheers
Sameer