why behavioural model of analog circuits are required for functional verification ?

[walkman]

why behavioral model of analog circuits for functional verification of mixed signal ip?

 

[rwender]

I'm going to assume that you are asking why behavioral models versus transistor-level models for analog circuits for functional verification...

Transistor-level models (SPICE models) provide high fidelity results but SPICE simulations are very compute intensive and therefore take quite sometime to run. And, when SPICE models are mixed with digital circuits (Verilog, VHDL behavioral) then two simulators must be "tied together" to run in lock step to perform the simulation. The synchronizing of these two simulators in a unified analog/mixed-signal (AMS) simulation slows things down as well.

Some people use SPICE macro-models (SPICE behavioral models) to reduce the complexity and speed up the simulation. This works but doesn't quite provide the necessary simulation speed-up required for system-level simulations.

Therefore, VHDL-AMS (VHDL with analog/mixed-signal extensions) and Verilog-A (Verilog plus analog) were created. A single simulation engine can support VHDL + VHDL-AMS simulations (same is true for Verilog + Verilog-A). This unified simulation backplane with behavioral mixed-signal modeling provides for simulations that run orders of magnitude faster than transistor-level simulations. For example, if you wanted to simulate one to two cycles of a sinewave being digitized by a sigma-delta analog to digital converter this could take 2-3 days in a SPICE + digital simulation. In fact, this is the kind of simulation that can crash your SPICE simulator unless you have a pretty expensive "industrial strength" simulation environment. The same sigma-delta simulation in a unified VHDL-AMS simulator can run in minutes.

Some examples of VHDL-AMS and Verilog-A design and simulation environments include:

ViaDesigner - **broken link removed**
SMASH - **broken link removed**
Symica - **broken link removed**

 

[LvW]

why behavioral model of analog circuits for functional verification of mixed signal ip?

For my opinion, each model is a "behavioral" model only. For example - this applies even to a simple resistor.
How do you model it in a simulation program? You are going to implement an equation that "models" the corresponding I-V "behavior".

 

[rwender]

Yes, even simple elements such as resistors and capacitors are modeled in VHDL-AMS. VHDL-AMS simulation environments come with libraries of models so you don't have to create all these models by hand. A VHDL-AMS model for a ideal resistor is shown below. You express V=I*R as the voltage across the port p1 and p2 with current flowing from port p1 to p2. A more detailed model of the resistor would contain Process, Voltage and Temperature (PVT) behavior.

-- Use proposed IEEE natures and packages
library IEEE;
use IEEE.electrical_systems.all;

entity resistor is

  generic (
    res : resistance);	-- Resistance (no initial value) [Ohm]

  port (
    terminal p1, p2 : electrical);

end entity resistor;

-------------------------------------------------------------------------------
-- Ideal Architecture (V = I*R)
-------------------------------------------------------------------------------
architecture ideal of resistor is

  quantity v across i through p1 to p2;

begin

-- Fundamental equation
[COLOR="#FF0000"]  v == i*res;
[/COLOR]
end architecture ideal;

 

[walkman]

I'm going to assume that you are asking why behavioral models versus transistor-level models for analog circuits for functional verification...

Transistor-level models (SPICE models) provide high fidelity results but SPICE simulations are very compute intensive and therefore take quite sometime to run. And, when SPICE models are mixed with digital circuits (Verilog, VHDL behavioral) then two simulators must be "tied together" to run in lock step to perform the simulation. The synchronizing of these two simulators in a unified analog/mixed-signal (AMS) simulation slows things down as well.

Some people use SPICE macro-models (SPICE behavioral models) to reduce the complexity and speed up the simulation. This works but doesn't quite provide the necessary simulation speed-up required for system-level simulations.

Therefore, VHDL-AMS (VHDL with analog/mixed-signal extensions) and Verilog-A (Verilog plus analog) were created. A single simulation engine can support VHDL + VHDL-AMS simulations (same is true for Verilog + Verilog-A). This unified simulation backplane with behavioral mixed-signal modeling provides for simulations that run orders of magnitude faster than transistor-level simulations. For example, if you wanted to simulate one to two cycles of a sinewave being digitized by a sigma-delta analog to digital converter this could take 2-3 days in a SPICE + digital simulation. In fact, this is the kind of simulation that can crash your SPICE simulator unless you have a pretty expensive "industrial strength" simulation environment. The same sigma-delta simulation in a unified VHDL-AMS simulator can run in minutes.

Some examples of VHDL-AMS and Verilog-A design and simulation environments include:

ViaDesigner - **broken link removed**
SMASH - **broken link removed**
Symica - **broken link removed**

Thanks for your excellent explanation.if you provide some pdf that would be great help for my thesis . my email id karthik.parigi@gmail.com