Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

why AWID signal is there when WID is removed from AXI4

Status
Not open for further replies.

abhinavpr

Junior Member level 2
Junior Member level 2
Joined
Jun 19, 2013
Messages
21
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
205
can anyone explain why AWID signal is there when WID is removed from AXI4. The explanation given is that AXI4 does not support write interleaving.

1. so if the write data has to be written in the order in which it arrives the whats the use of AWID?

2. in a scenario where a slave receives write data from multiple master and supports outstanding operation , how will it receive the data and response in the absence of wid
 

the WDATA is not interleaving so the order of WDATA is the SAME witn the order of AW. Get the WDATA and AW together from the outstanding queue. when the WID is present in the old AXI version, a WDATA re-order mechanism will be inferred, and thanks to the remove of WID, we do not need that mechanism any longer.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top