abhinavpr
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can anyone explain why AWID signal is there when WID is removed from AXI4. The explanation given is that AXI4 does not support write interleaving.
1. so if the write data has to be written in the order in which it arrives the whats the use of AWID?
2. in a scenario where a slave receives write data from multiple master and supports outstanding operation , how will it receive the data and response in the absence of wid
1. so if the write data has to be written in the order in which it arrives the whats the use of AWID?
2. in a scenario where a slave receives write data from multiple master and supports outstanding operation , how will it receive the data and response in the absence of wid