why and when do we need to ignore timing analysis of paths uinsg TIG?

[syedshan]

Hi

I think the question is self explanatory.

I cannot understand when to apply this (one case is of course when we see that some path is not critically important for timing, I guess?)

I am having setup problems with my design that is using MIG and the problem occurs in the MIG, since I use the vendor design as my reference hence in the UCF file I have found the timing ignorance commands like

#TIMESPEC TS_CLK_synth_7 = FROM "clk125_B0p_0" TO "sip_clkrst_fm680_0_i_clkrst_fm680_clk_buf_inst_clkout2" TIG;
#TIMESPEC TS_CLK_synth_8 = FROM "clk125_B0p_0" TO "sip_clkrst_fm680_0_i_clkrst_fm680_clk_buf_inst_clkout1" TIG;
#TIMESPEC TS_CLK_synth_9 = FROM "clk125_B0p_0" TO "sip_clkrst_fm680_0_i_clkrst_fm680_clk_buf_inst_clkout0" TIG;

#TIMESPEC TS_CLK_200m_0 = FROM "clk125_B0p_0" TO "sip_clkrst_fm680_0_i_clkrst_fm680_clk_200_inst_clkout0" TIG;
#TIMESPEC TS_CLK_200m_1 = FROM "sip_clkrst_fm680_0_i_clkrst_fm680_clk_200_inst_clkout0"  TO "clk125_B0p_0" TIG;

as an example...


so I was wondering if I can trace back why do they ignore these timings.

bests
Shan

 

[syedshan]

any one reply...
in need stuck with timing analysis errors...

 

[mrflibble]

Well, for one thing I noticed that for some xilinx generated fifo's you also better had use TIGs. It's in the docs somewhere and also at a random location in some of my notes. So that's another example of vendor provided TIG constraints similar to this one. And this looks like: ignore the relationship between <several_signals> and a specific reset signal.

 

[aruipksni]

Hi

I think the question is self explanatory.

I cannot understand when to apply this (one case is of course when we see that some path is not critically important for timing, I guess?)

I am having setup problems with my design that is using MIG and the problem occurs in the MIG, since I use the vendor design as my reference hence in the UCF file I have found the timing ignorance commands like

#TIMESPEC TS_CLK_synth_7 = FROM "clk125_B0p_0" TO "sip_clkrst_fm680_0_i_clkrst_fm680_clk_buf_inst_clkout2" TIG;
#TIMESPEC TS_CLK_synth_8 = FROM "clk125_B0p_0" TO "sip_clkrst_fm680_0_i_clkrst_fm680_clk_buf_inst_clkout1" TIG;
#TIMESPEC TS_CLK_synth_9 = FROM "clk125_B0p_0" TO "sip_clkrst_fm680_0_i_clkrst_fm680_clk_buf_inst_clkout0" TIG;

#TIMESPEC TS_CLK_200m_0 = FROM "clk125_B0p_0" TO "sip_clkrst_fm680_0_i_clkrst_fm680_clk_200_inst_clkout0" TIG;
#TIMESPEC TS_CLK_200m_1 = FROM "sip_clkrst_fm680_0_i_clkrst_fm680_clk_200_inst_clkout0"  TO "clk125_B0p_0" TIG;

as an example...


so I was wondering if I can trace back why do they ignore these timings.

bests
Shan

Try to lower your clock rate. You must be having a hardware design problem.