You should not tell your story as . Because this is not a talent of Red Hat Girl . Instead of this , you should prepare a document that explains the evolution of the story and other datas.. etc. And then we can be helpful to you.mesfet said:Hi all,
I'm just a newbie in rfic design. Can anyone share with us the experience in designing rfic? For eg, tutorials on using the messy cadence, pitfalls that should be avoided in design, layout techniques......etc.
I'm now encountering a problem in my design. Any suggtestions are welcome. I've designed a single stage amplifier with 0.6um technology of AMS. Inductor are designed by asitic, the simulated and measured data does match well. Both input and output matching are off-chip and are load-pulled for maxium gain. But the problem is that gain of the amplifier drop from 14dB to only 5dB!! My conclusion is that there is any ground in the cmos chip. There is an inductance between ground of my cmos chip and the "true" ground of my PCB board, this inductive feedback lower gain of my amplifier. Am I correct? Anyone have suggestions on raising gain of my amplifier? I've tried 3 bond wires in parallel but not much benefit is gained.