while loop depending on an input argument

now this is a very basic question:

The code seen below goes to infinite loop during synthesis, hence my sythesis tool halts (with an error like, "loop has iterated 64 times so i am halting blah blah"). The reason behind this is that "data" is assigned to X (undefined-unknown) and the evaluation (i<data) yields X, and a while loop executes if its condition is X.

Isn't this an apparent problem? Am i missing some point? What is the workaround?


module example(data, trig)

input [4:0] data;
input trig;
output out;
reg out;
integer i;

always @ trig
begin

out=0;
i=0;
while(i<data)
begin
out=~out;
end

end

endmodule


I just need a loop which runs until it hits a variable number given by the user, not until a constant predefined value..

How to?

hi
While loop is not synthesiable
Please re-write your code using synthesiable conditional statement

thanks
haytham

Hi.
Try this one.
Use a LOAD signal to load the value.

module example(data, trig,load)

input [4:0] data;
input trig,load;
output out;
reg [4:0] value;
reg out;
integer i;

always @ trig
begin

out=0;
i=0;
if(load)
value = data;
else
while(i<value)
begin
out=~out;
end

end

endmodule