Hi ramesh,
The reason is there will be cells present in both paths so that its violation. we can easily pick that cells by fanout if the fanout is high it will affect other paths too.. So upsize or downsize the cells which is independent to that path. Also look the path is from which clock to which clock(whether it can be set to false path or multicyle path) .
To fix this setup violation.
if its reg to reg path try to add buffers on the clock pin.
in to reg or reg to out or in to out delete unwanted buffers.