Which tool can verify functional equivalence if given two different netlist files?

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ipelagic

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Dear All,
I am a newbie to ic design. My question is that if I were provided with two designs. ( All written in VerilogHDL ) Is there any tool supported by Synopsys or Cadence that can help me to verify the equivalence of these two designs?
One design is in a .v file. And the other is split into several submodule (.v files) along with a top module ( _top.v ). I think there should exist a tool to help me verify the equivalence if given IN/OUT PIN mapping. Thanks in advance
 

equivalence check can be done with formality from synopsis and verplex from cadence
 
I would like add one more tool that is adopted by the industry as the best signoff tool thats is cadence conformal. i would encourage you to refer to its docs/userguides. for better understanding of the concepts.

Cheers
 

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