Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Which tool can verify functional equivalence if given two different netlist files?

Status
Not open for further replies.

ipelagic

Newbie level 3
Joined
Jun 22, 2012
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,303
Dear All,
I am a newbie to ic design. My question is that if I were provided with two designs. ( All written in VerilogHDL ) Is there any tool supported by Synopsys or Cadence that can help me to verify the equivalence of these two designs?
One design is in a .v file. And the other is split into several submodule (.v files) along with a top module ( _top.v ). I think there should exist a tool to help me verify the equivalence if given IN/OUT PIN mapping. Thanks in advance
 

equivalence check can be done with formality from synopsis and verplex from cadence
Dear All,
I am a newbie to ic design. My question is that if I were provided with two designs. ( All written in VerilogHDL ) Is there any tool supported by Synopsys or Cadence that can help me to verify the equivalence of these two designs?
One design is in a .v file. And the other is split into several submodule (.v files) along with a top module ( _top.v ). I think there should exist a tool to help me verify the equivalence if given IN/OUT PIN mapping. Thanks in advance
 
I would like add one more tool that is adopted by the industry as the best signoff tool thats is cadence conformal. i would encourage you to refer to its docs/userguides. for better understanding of the concepts.

Cheers
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top