It is clear from the replies here that many of you have not done a real chip design. You do need a "seed" sdc file which defines clocks and input/output delays for the synthesizer. It should also have false paths, multicycle paths, and generated clocks. After synthesis you generate a NEW sdc from DC, you get many new paths generated, lots of nets. You run Primetime on this netlist and read in that sdc. After all the false timing paths have been analyzed and constraints are updated, you write a new sdc which is given to PnR. Primetime is run several times: post-synth, after FloorPlanning & Global PnR, after CTS & Detailed Route, and after Parasitic extraction.
Rajat Sewal