I'm currently using Synplify from Synplicity and LeonardoSpectrum from Mentor but i can't make my design work properly at every try because of the timing constraint and the bad optimiser. My target is a FLEX10k130e FPGA running at 60MHz. Any advice would be helpfull...
Sorry to say it, but if you can't get your desgin to work with synplify or leonardo, then there is something wrong with your design, not the compilers.
Take a second look at your code.
I'm using Synplify Pro with a 1.5 million gate design and it optimizes excellently.
1)Same as Pissant said on your question.
2)I'm using both the Synplify and Leonardo,
but i like the Synplify than to
the Lonardo in my projects.
(0.4~1 million gate count)
I use Synplify_pro here.
There're some problem in release v7.0 .
I have no idea if the new release have fixed
these problem.
Otherwise the v6.24 work well in all aspect.
Ok, right, i have "only" about 70k gates... I have actually pb with clock skew... So i'll need to try "Amplify" ? Is that from Synplicity too ?
Btw, i found that there are way less options in Synplify rather than in Leonardo Spectrum.
I have Symplify 7.0.2, shoud i try the 6.2 version ?
Thx a lot :smile:
What Amplify do is just to write the constraint to guide the P&R tool to meet
requirement. If u partition ur block carefully. May it can help u to reduce
the clock skew locally.
If FPGA's limited clock tree resource( i think 4 in xilinx) is the problem's source.
U have only the slow routing resource. May u think to change the design to use the negative and positive together to avoid the setup/hold timing check problem.
And the slack may worse due to half clcok period required time.
Or consider to use the asynchronous technique (2 flip-flop , hand-shake etc.)in deal with the same clock domain but in different latency to relief clock skew requirement.
I use synplify pro 7.0.3 to compile my project, the compiler complain a strange error.
With version 6.2.4, everything is good.
btw, my project is write in VHDL.
I think in version 7.0.3, some bug exist.
The original question was to make a code work at 60MHz. KTe: I used the same device and it can easily work over 75 MHz just by avoiding big equations and use clever pipelining. Do not forget that the logic cells in the FPGA you are using have only 4 inputs (plus a nice carry/cascade input). In short, make your equations simplers. Run the Timing Analyser to display the critical paths if nothing seems wrong in the Sy*pli*fy report file and cut big combinatorial equations into smaller clocked ones!
BTW, I agree with all of you that Sy*npli*fy and Am*pli*fy are the best tools to use (eventhough I did not require Am*pli*fy yet... maybe with my current 2M gate design... TBD).
Clock skew isn't the main problem (in 99.% of the cases not a problem at all) in FPGA design.
For example in Xilinx Virtex-E (not the newest FPGA on the shelf) the m@ximum clock skew if using the global clock recourses is less than 300 ps.
This means that if your clock frequency is 100 MHz less than 3% of your timing budget is spent on clock skew.
Your timing budget is consumed by logic delay (40 - 60 %) and routing delay (40 - 60 %).
Synplify (and Leonardo and design compiler etc) try to reduce your logic delay by breaking your HDL description into clever bolian equations.
Amplify is trying to help the PAR tool to place the logic elements in a more clever way so the routing delay will be reduced.
75 MHz should be achievable in a modern FPGA (like the one you are using). To do that you must first understand if your problem comes from routing delay (use Amplify , RLOCs or florplannig) or from logic delay (modify your design , many techniques, the simplest is pipelining that break up your combinatorial paths).