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Which synthesis tool to use with a FPGA ?

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KTy

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I'm currently using Synplify from Synplicity and LeonardoSpectrum from Mentor but i can't make my design work properly at every try because of the timing constraint and the bad optimiser. My target is a FLEX10k130e FPGA running at 60MHz. Any advice would be helpfull...

KTy
 

pissant

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Sorry to say it, but if you can't get your desgin to work with synplify or leonardo, then there is something wrong with your design, not the compilers.

Take a second look at your code.

I'm using Synplify Pro with a 1.5 million gate design and it optimizes excellently.
 

code2000

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1)Same as Pissant said on your question.
2)I'm using both the Synplify and Leonardo,
but i like the Synplify than to
the Lonardo in my projects.
(0.4~1 million gate count)

____________________
Best regards,
code2000
 

simon2kk

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I use Synplicity for Xilinx design.

it is a better and leading tool in the market.
 

jackymiso

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Dear,

I use simplfy pro and leonardo.

If you can't operate your design properly,

It is generally clock skew problem.

So, you must optimize your HDL codes and use amplify for the detail optimization.

Thanks...
 

Nobody

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I use Synplify_pro here.
There're some problem in release v7.0 .
I have no idea if the new release have fixed
these problem.
Otherwise the v6.24 work well in all aspect.
 

KTy

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Ok, right, i have "only" about 70k gates... I have actually pb with clock skew... So i'll need to try "Amplify" ? Is that from Synplicity too ?
Btw, i found that there are way less options in Synplify rather than in Leonardo Spectrum.
I have Symplify 7.0.2, shoud i try the 6.2 version ?
Thx a lot :smile:

KTy
 

yeewang

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With Amplify, you can get 10-20% improvement. Good luck.
 

joace

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i have used FPGA express,simplfy pro and leonado,i think sim is best.
 

Nobody

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What Amplify do is just to write the constraint to guide the P&R tool to meet
requirement. If u partition ur block carefully. May it can help u to reduce
the clock skew locally.
If FPGA's limited clock tree resource( i think 4 in xilinx) is the problem's source.
U have only the slow routing resource. May u think to change the design to use the negative and positive together to avoid the setup/hold timing check problem.
And the slack may worse due to half clcok period required time.
Or consider to use the asynchronous technique (2 flip-flop , hand-shake etc.)in deal with the same clock domain but in different latency to relief clock skew requirement.
 

zzxxdd

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i think amplify is better, leo is too simple if someone else want do some complex work it's better to use amplify or synplify pro
 

buzkiller

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Amplify is the only tool on the market that can do physical synthesis. Go for it, if you can afford it. Otherwise use Synplify Pro.

If you do choose Amplify, then don't just rely on physical synthesis, floorplan your design
(always a good idea).

regards,
Buzkiller.
 

prisnow

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I think synplify_pro is better.
 

marsgod

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I use synplify pro 7.0.3 to compile my project, the compiler complain a strange error.
With version 6.2.4, everything is good.
btw, my project is write in VHDL.
I think in version 7.0.3, some bug exist.
 

TurboPC

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The original question was to make a code work at 60MHz. KTe: I used the same device and it can easily work over 75 MHz just by avoiding big equations and use clever pipelining. Do not forget that the logic cells in the FPGA you are using have only 4 inputs (plus a nice carry/cascade input). In short, make your equations simplers. Run the Timing Analyser to display the critical paths if nothing seems wrong in the Sy*pli*fy report file and cut big combinatorial equations into smaller clocked ones!

BTW, I agree with all of you that Sy*npli*fy and Am*pli*fy are the best tools to use (eventhough I did not require Am*pli*fy yet... maybe with my current 2M gate design... TBD).
 

fpga_master

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Just to clarify:

Clock skew isn't the main problem (in 99.% of the cases not a problem at all) in FPGA design.
For example in Xilinx Virtex-E (not the newest FPGA on the shelf) the m@ximum clock skew if using the global clock recourses is less than 300 ps.
This means that if your clock frequency is 100 MHz less than 3% of your timing budget is spent on clock skew.
Your timing budget is consumed by logic delay (40 - 60 %) and routing delay (40 - 60 %).
Synplify (and Leonardo and design compiler etc) try to reduce your logic delay by breaking your HDL description into clever bolian equations.
Amplify is trying to help the PAR tool to place the logic elements in a more clever way so the routing delay will be reduced.
75 MHz should be achievable in a modern FPGA (like the one you are using). To do that you must first understand if your problem comes from routing delay (use Amplify , RLOCs or florplannig) or from logic delay (modify your design , many techniques, the simplest is pipelining that break up your combinatorial paths).

Hope it helps,

F.M.
 

cuiyujie

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Problem is from your large combinational logic for sure, check your own code and synthesis result, analyze your critical path, you can make it.
 

phone

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Use more flops and try to use pipeline concept. As these FPGA are generally very bad to do combinational logic.
 

freeinthewind

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i think pissant is right . i use Synplify Pro to optimize my design . it works very well.
 

wkong_zhu

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If you use synopsys DC as ASIC synthesis.
Then DCFPGA is a tool for FPGA synthesis.
You can use DCFPGA if you can use DC.
 

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