28.7% (in mW) more dynamic power consumed by Synchronous Reset design versus Asynchronous Reset design.
18% (in uW), more leakage power consumed by Asynchronous Reset design.
These are the results when running report_power from Synopsys Design Compiler
Asynchronous Reset Design, 90 nm, 200+ MHz
====================
****************************************
Report : power
-analysis_effort high
Design :
Version: X-2005.09-SP2
Date : Wed Jun 20 10:17:08 2007
****************************************
Library(s) Used:
g90d
g90ld
Operating Conditions: WC Library: g90d
Wire Load Model Mode: enclosed
Global Operating Voltage = 0.9
Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 1.000000pf
Time Units = 1ns
Dynamic Power Units = 1mW (derived from V,C,T units)
Leakage Power Units = 1mW
Cell Internal Power = 22.9686 mW (74%)
Net Switching Power = 7.9670 mW (26%)
---------
Total Dynamic Power = 30.9356 mW (100%)
Cell Leakage Power = 1.0090 mW
****************************************
Report : clock_gating
Design :
Version: X-2005.09-SP2
Date : Wed Jun 20 10:14:17 2007
****************************************
Clock Gating Summary
------------------------------------------------------------
| Number of Clock gating elements | 169 |
| | |
| Number of Gated registers | 6203 (72.45%)
|
| | |
| Number of Ungated registers | 2359 (27.55%)
|
| | |
| Total number of registers | 8562 |
------------------------------------------------------------
****************************************
Report : area
Design :
Version: X-2005.09-SP2
Date : Wed Jun 20 10:14:18 2007
****************************************
Library(s) Used:
g90d
g90ld
g90fd
Number of ports: 1484
Number of nets: 1569
Number of cells: 54
Number of references: 13
Combinational area: 290679.656250
Noncombinational area: 201757.390625
Net Interconnect area: 246920.203125
Total cell area: 492459.406250
Total area: 739379.625000
1
Synchronous Reset Design, 90 nm, 200+ MHz
====================
****************************************
Report : power
-analysis_effort high
Design :
Version: X-2005.09-SP2
Date : Tue Jun 19 19:04:20 2007
****************************************
Library(s) Used:
g90ld
g90d
Operating Conditions: WC_SA Library: g90d
Wire Load Model Mode: enclosed
Global Operating Voltage = 0.9
Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 1.000000pf
Time Units = 1ns
Dynamic Power Units = 1mW (derived from V,C,T units)
Leakage Power Units = 1mW
Cell Internal Power = 30.8147 mW (77%)
Net Switching Power = 9.0087 mW (23%)
---------
Total Dynamic Power = 39.8234 mW (100%)
Cell Leakage Power = 848.4954 uW
****************************************
Report : clock_gating
Design :
Version: X-2005.09-SP2
Date : Tue Jun 19 19:01:27 2007
****************************************
Clock Gating Summary
------------------------------------------------------------
| Number of Clock gating elements | 165 |
| | |
| Number of Gated registers | 6053 (72.86%)
|
| | |
| Number of Ungated registers | 2255 (27.14%)
|
| | |
| Total number of registers | 8308 |
------------------------------------------------------------
****************************************
Report : area
Design :
Version: X-2005.09-SP2
Date : Tue Jun 19 19:01:27 2007
****************************************
Library(s) Used:
g90ld
g90d
g90fd
Number of ports: 1476
Number of nets: 1535
Number of cells: 28
Number of references: 9
Combinational area: 261496.671875
Noncombinational area: 166909.062500
Net Interconnect area: 208199.640625
Total cell area: 428412.812500
Total area: 636612.437500