Which Op-Amp Architecture is suitable for 1.5 bit/stage in pipelined ADCs

[Rezaa]

Hey guys, I am wondering which architecture is suitable to design 1.5 bit/stage for Pipeline ADCs, specifically I wanna design a 12-bit pipeline ADC in 90nm CMOS technology and I would be appreciate if anyone can have some guideless. I think it's better to make it using by ten 1.5 b stages and a 2 bit flash at the end. and right now I wanna design the first 1.5 b stage.

 

[Dominik Przyborowski]

You will need high gain opamp, maybe telescoping cascode with gain boosting be enough to obtain good resolution.

 

[Rezaa]

Thank you for answering, Dominik, I've designed a two-stage op-amp, a bad one in frequency response and I will design a telescopic cascade with gain boosting for next but always I had some critical doubts about some definitions, and I am confused about:
1. the min/max available input of ADC (stages) is related to min/max of op-amp? how is it going (I've studied main references so many times)
2. in Switched Capacitor circuits (such MDAC in 1.5 b stage, S/H) our op-amp would be biased to be always on having input cm level to make that happened or not? we just make the SC circuit and give the input and it works by itself? I don't know I'm just confused how does it work really in switched capacitor circuits
3. rest of my problems are in the next part of the design and I'll ask them at the day that I've passed the currents...

 

[Rezaa]

OK!!
how to estimate ota targets of design? especially for a 12b pipeline adc using 10 1.5bit/stage
HOW MUCH GAIN
HOW MUCH BANDWIDTH
HOW MUCH LOAD CAPACITOR
oh god would you please anyone share some experience? that's why edaboard.com does exist isn't it? if I'm wrong let me know.

 

[erikl]

OK!! ;-) There's so much literature so simply to be found about this issue.

 

[Rezaa]

Anyway, thanks, I almost have eaten google, ieee, refrences and I am just not capable enough because my designing skill should grow only by experience and what I said here was just the need of sharing some experience for a little guide almost I'm pretty sure that I am not lazy at all to not knowing Google.Com is an easy way to search because I can just walk for month even if I had no any hope to find some signs but I just do whatever I can do, I've my chance to try.

 

[erikl]

how to estimate ota targets of design? especially for a 12b pipeline adc using 10 1.5bit/stage
HOW MUCH GAIN
HOW MUCH BANDWIDTH
HOW MUCH LOAD CAPACITOR

Reeza, these questions can only be answered by yourself, because they depend on your application - and you didn't yet reveal the necessary parameters:

GAIN depends on your input voltage: closed loop gain = max. ADC input voltage / max. input voltage from outside. In order to keep the necessary accuracy, the open loop gain should be at least by a factor of 2ⁿ higher than the closed loop gain for the necessary amplification of your input signal, i.e. at least by a factor of 4096 in your 12b case, and this over the full required bandwidth of your input signal.

BANDWIDTH depends totally on the bandwidth of your input signal, or of that part you are required to convert in your application.

LOAD CAPACITOR value should be nominated by the customer of your ADC - you have to take care that your ADC can drive it without accuracy loss - which in case of an ADC is simple, because it consists of digital output.

 

[Rezaa]

Thank you @erikl for your helpful answer, I would be appreciate if you (or any other gentleman or lady that is reading this, thanks to my honor) tell me somethings additionally,
After compensation of unity gain buffer to our desired phase margin is it important to be sensitive about the destiny of the shape of the phase diagram in higher frequencies than Wta? for example if we have Wta=600Mhz does it matters that phase diagram is rising for example at 2GHz(unstable at higher frequencies)? I just like to know.
Also for best performance I've considered 60 degree of phase margin, do we have agreement about this choice?
I have third question after all that I'm not proud of asking that, for compensation I've used CL=0.11p, i just am confused when i use the OTA in my general circuit as a black box and using for example 1p load capacitance for S/H does this load capacitance have any effect on my compensation? Should I choose load capacitance due to that CL that i used in my OTA, I guess you figured out that how confuse am about what, would you please poke my observations.

 

[erikl]

... if we have Wta=600Mhz does it matters that phase diagram is rising for example at 2GHz(unstable at higher frequencies)?

If Wta is the same as UGB (Unity Gain Bandwidth) this doesn't matter (and rising phase not at all, anyway).

... for best performance I've considered 60 degree of phase margin, do we have agreement about this choice?

Sure!

... when i use the OTA in my general circuit as a black box and using for example 1p load capacitance for S/H does this load capacitance have any effect on my compensation?

Only at high frequencies ≦ UGB, where the feedback compensations tends to change more and more into a feed forward path (because of the low gain in this frequency region). Here, Cc and CL work as voltage divider, which means your UGB will be reduced with larger load capacitances CL. You can easily analyze this effect by ac open loop simulation.