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[SOLVED] Which one is the best VHDL/Verilog Synthesis tool for FPGA/A

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best synthesis tool

I am not familiar with ASIC design flow, maybe somebody else can give some valuable comments....

For FPGA design, what I have used synthesis tools(only to synthesis VHDL code): Synplicity Synplify > Synopsys FPGA Compiler II > Mentor Leonardo Exemplar
It is only my personal opinion...
 

andy2000a

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leonardo exemplar

On 2001-07-13 23:19, chc wrote:
I am not familiar with ASIC design flow, maybe somebody else can give some valuable comments....

For FPGA design, what I have used synthesis tools(only to synthesis VHDL code): Synplicity Synplify > Synopsys FPGA Compiler II > Mentor Leonardo Exemplar
It is only my personal opinion...
for FPGA
synplicity > FPGA express > exemplar

for ASIC
cost /performance ration
Cadence Ambit > ?? I forget > Synopsys
DC
I never try synplicity ASIC
 

cdic

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I don't think so, for FPGA the sequence is reasonable, but for ASIC, I think the DC is the best.
 

CatKing

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DC on unix is best, on PC is worst
 

nmtr

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if you are new learner,i suggest you to try the Men*or's Leonardo,it can not only synthesis fpga but ASIC, with friendly interface ,and ease to use. it will guide you to master HDL quickly.(this tool will give you the RTL and Cell map to guide you understand your project and HDL source).
so my suggest is:
for new learner:exemplar > synplicity>FPGA express
for master :Synopsys DC > Cadence Ambit > exemplar
 

cdic

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DC on Linux and Unix is the best. on WinNT I don't know. cause all of my eda enviroment is based on Linux home
 

formatrix

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I think DC is the best than others.
 

xmizi

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Synopsys DC has full-fledged logic optimization algorithm than others. Also it provides good interface to backend tools such as Floorplan Manager. A lot of backend P&R tools such as Avant!'s Apollo uses DC's sdc(synopsys delay constraint) format for timing driven place and route.
 

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