as far as I know the hardware will depend on many things. For instance, on the cells library and on the constraints file which are both inputs to the logic synthesizer.
However, my guess is that both "? :" and "if else" will generate the same hardware if they are synthesized with the same .lib and .sdc files.
As far as synthesis to hardware, there is no functional difference between the conditional operator and the if/else statement. The conditional operator can be nested in other expression so that you do not need intermediate variables, so it is more compact. However, that can make it more difficult for others to read your code. SystemVerilog add a few additional flavors of if statements (unique-if/priority-if)that can influence how the if statement gets optimized.
There is a difference between the two constructs when it comes to X-propagation in logic simulation, specifically the case where 'foo' is unknown. The subject of X-propagation during dynamic simulation is a deeply technical and controversial subject. Just search for 'Verilog X-propagation'
But I have another doubt for mux as you talked about X-propagation.
S A0 A1 o/p
1) X 0 0 0 -- no doubt as schematic is also working as per truth table
2) X 1 1 1 -- Doubt : As hardware perspective, S=X means S=1 or S=0, in both case the output is 1.
But in simulation if we check it through the gate level of mux than output is X but hardware perspective it is 1. So is there any specific reason why this happens? or how can we prove it for simulation?
As Liffs points out, there is only one representation of X in a Verilog (or VHDL) simulation. You really need some sort of formal analysis so that when an X value re-converges, you know that the two X's in your equation are identical values, even though you do not know its value.