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which of the follow circuits can generate glitch free gated_

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littlefield

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which of the follow circuits can generate glitch free gated_clk?

A.always@(posedge clk) gated <=en;
assign gated_clk=gated&~clk;

B.always@(negedge clk) gated <=en;
assign gated_clk=gated&~clk;

C.always@(posedge clk) gated <=en;
assign gated_clk=gated|~clk;

D.always@(negedge clk) gated <=en;
assign gated_clk=gated|~clk;

this is an interview question, but I don't think any of above answer is corect, Am I wrong?
 

sameer_dlh25

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Re: which of the follow circuits can generate glitch free ga

Hi littlefield,

I think B answer is correct.

This will make sure 'en' always changes in inactive duration of the clock :D
 

littlefield

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Re: which of the follow circuits can generate glitch free ga

____------____------____------____------____clk

------____------____------____------____------~clk

------------------------_____________________en

-----____------____X____________________gate_clk

if choose B
I think it will have the glitch at the point X,
at this time, (~clk) change from low to high, en change from high to low.
if we do RTL simulation, it haven't glitch
but we do the post-layout simulation, it probably have glitch
 

rakesh1234

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Re: which of the follow circuits can generate glitch free ga

A is the answert
 

littlefield

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Re: which of the follow circuits can generate glitch free ga

____------____------____------____------____clk

------____------____------____------____------~clk

___________________-----------------------en

___________________x___------____------gate_clk

if choose A
I think it will have the glitch at the point X,
at this time, (~clk) change from high to low, en change from low to high.
if we do RTL simulation, it haven't glitch
but we do the post-layout simulation, it probably have glitch
 

nemolee

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Re: which of the follow circuits can generate glitch free ga

Your interview question must have a precondition.
en is synchronous with clk and have a little phase shift.
If no this precondition, this design must have clock domain crossing mechanism.
 

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