Which logic is better with respect to hardware implemetation

[imbichie]

Hi all,

Please check the below two verilog codes and please let me know, whether the hardware implementation of both codes are same or not?
If not same which is the better logic.

Logic 1:

always @ (posedge clk or negedge rst)
  begin
     if (~rst)
       a <= 1'b0;
    else if (b)
       a <= ~a;
  end

Logic 2:

always @ (posedge clk or negedge rst)
  begin
     if (~rst)
       a <= 1'b0;
    else if (b && ~a)
       a <= 1'b1;
    else
      a <= 1'b0;
  end

The logic of the codes is like this, under active low rst the value of a is low and when the b is high the value of a became low in the first clock and became high in the 2nd clock. (The behavior of signal b is like this : whenever the b is high, its high for even number of clock, means b can be high for continuously either 2,4,6,8,...2n etc clock cycles ).

 

[rca]

logic 1, "a" =1 when posedge of clk and b=1, that is different you wrote, no?
why, you not just said a<=b at posedge of clk? if b is also from the same clock.

 

[ads-ee]

Given the behavior of b is defined as being high for two clocks starting with a low, both should behave the same. If b were to somehow misbehave the results of the two implementations will differ. As the behavior of b is likely to not be taken into account by a synthesis tool the two descriptions will likely have different gate level results.

Regards,

 

[imbichie]

Hi,
Thanks to all your reply.
my intention is to make the signal a from b, just like below.

clk __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__
b __|------------|____|------------------------|___________|-----------|_____
a ________|-----|__________|-----|_____|-----|________________|-----|_____

So whether the two logic have same hardware or different, which is better?