Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Which language is beeterr for designing FPGA, VHDL or Verilog?

Not open for further replies.


Full Member level 5
Mar 31, 2002
Reaction score
Trophy points
In the warm company of God's most exquisite creati
Activity points
Hi all,
I am researcher who is getting to know the basics of HDL now.I would like to know whether to learn VHDL or Verilog.My requirements are
that it should help me to rapidly design FPGA based controllers for my job.
Of course it should be easy to learn.In this regard which one should I try to study ? Thanks a lot.

That nobody can say you!


I'm sorry but that can nobody say you! I'm programming VHDL for over 5 years. When I see a Verilog source I understand it also! I think if you understand one of these languages you need not long to switch between them.
When you want to start with HDL I think it make no difference if you start with VHDL or Verilog. In Europe (~75%) the companys use normally VHDL in the USA (80%) they use Verilog. VHDL is IEEE certificated and I think Verilog not.
I hope that help you for your choice!!


Verilog is popular in USA and Japan, while VHDL in Europe (e.g. ESA or spin-off companies that deliver IPs).

Personally, i prefer VHDL. I started with Verilog but this language lacks some useful constructs, e.g. multi-dimensional arrays. On the other hand, it you get to write useful code earlier in Verilog thatn VHDL.

VHDL is better for "coding for reuse" thta is developing IPs to be used in SOCs. However, there are skillful engineers in both sides. Or that use both languages.


I have been coding in HDL for about 6 years. First year I have used VHDL, but after that I switched to verilog, mainly because I’m more productive by using verilog. Code written in verilog is about halve the size of VHDL code and from my point of view is clearer and simpler to understand and easier to debug. This is why I was able to find bugs much quicker in verilog. I’m designing exclusively for Xilinx FPGAs (Virtex, Virtex-II). Many verilog drawbacks, including the one pointed out by the_penetrator, were eliminated with the new revision of Verilog “standard” (verilog 2001). If you are a new to HDL, I suggest you to start with verilog.


vhdl or verilog

IMHO, if you have expierence in C programming, best start from verilog. Verilog syntax like C, VHDL like ADA. But may be for FPGA design for you better use schematic entry?

VHDL or Verilog

I have lots of war stories from the founding of Chronologic (June
1991). You wouldn't believe the number of "industry experts" who told
me that I was either wasting my time producing a Verilog simulator, or
that it might be an interesting short-term opportunity, but in 3 years
the world would be VHDL. It was literally everyone who makes a living
at prognosticating the EDA business.

Why is the design community more solidly Verilog-oriented than ever?
What happened (or didn't happen) to make these predictions wrong?
While people in this group generally look for technical differences
in the languages, if you look at the business situation (that is,
money), it is clear that there is one winner in this "war", and that
is Verilog. Companies developing new products go where the money is,
and the money is overwhelmingly in the Verilog part of the market. The
last numbers (from Dataquest, no less) have Verilog products
outselling VHDL products by more than 2-1 (in revenue, not licenses),
and the real difference is almost certainly higher.

My own opinion of the fundamental reason for Verilog's staying power
is that Verilog had a very large head start in number of engineers who
knew Verilog before VHDL really got out of the blocks, and Verilog is
easier to learn than VHDL. Thus, the established designers already
knew Verilog, and had no reason to learn VHDL, and the new designers
could pick it up easier than they could pick up VHDL.

You can argue all you want about the technical merits of the two
languages, and the "understandability" of each. I know that I
personally learned Verilog in a very short period of time. Later, when
I decided that I really should learn VHDL in order to be able to
market my product against it, I found that learning VHDL really was
harder. I'm sure I've spent more effort trying to learn VHDL than I
did in the early days of my Verilog use, and I'm only barely literate
in VHDL. (Admittedly, I'm a little handicapped in that I never learned
Ada, but C wasn't my first (or even second or third) language,

When you couple this lower barrier to using Verilog with the fact that
there is really no good reason to switch from Verilog to VHDL (and
until VITAL there were good reasons to switch from VHDL to Verilog),
it is easy to see why the market didn't move the direction the pundits
believed it would.

quote from my friend's e-mail

Verilog vs VHDL

some article on language comparation

Verilog Popularity

An article comparing Verilog and VHDL and Verilog's


You are obviously a `verilog' guy producing verilog tools, so I understand your biased view.

I believe that the main reason there are so many verilog tools on the market is that it's *extremely* difficult to write a complete VHDL parser and semantic analysis. No one has complete parser and semantic analysis as far as I know.

Another problem are ambiguities in VHDL syntax - this has no real importance in practice, even for power-users, but it makes tool development a very painful experience.

Creating a tool for verilog is much much easier.

Now about my opinion...

It's true that verilog has steeper learning curve, in the beggining. But if you want to write more advanced code, you have to use PLI - and that's a hassle.

For example, you can't even simulate large memories in verilog!! - it's so easy to do it in VHDL.

So VHDL is slower to learn at the beginning but you reach advanced stuff faster.

Verilog simulation behaviour is not very well defined. As Bergeron says: "I yet have to see two verilog simulators producing the same result".

For verification, both languages are crippled, but VHDL a bit less. SystemVerilog could change that, I admit.


Re: VHDL or Verilog

tahiti said
For example, you can't even simulate large memories in verilog!! - it's so easy to do it in VHDL.

Why cannot simulate large memories in Verilog ?
I don't understand !
May you explain or give an example ?

Thanks in advance :eek:

Re: VHDL or Verilog

verilog or VHDL a big question normally asked? which one to choose. historically speaking VHDL was developed by the defence sector and was based on ADA. then the industry people argued that why to use VHDL it hard for them to use. an alternative was made and verilog was developed, very much like C/C++.

VHDL is powerful in terms of control its power is just like power in assembly and for verilog its like C/C++ you don't have to write very much for so much smaller things. but do u really need that much control?

the text of VHDL is very complicted, where as for verilog its just like C/C++ easy to learn just in 2-3 days if u know C/C++.

lerning VHDL or verilog depends upon which environment u are surviving?

but the things u mentioned are it must be fast and easy to learn and the applications u mentioned i will suggest go for verilog thats easy and no problem to learn that.

i am a beginner of HDL, and i learn VHDL first, but now i use verilog because i feel it is more easy to learn.

Re: VHDL or Verilog

Verilog is going to be the winner, especially with the release of 2001
and SystemVerilog. Already, $ynopsys is giving indication that it
will support Verilog more than VHDL. All VHDL tool accept Verilog now,
which was not the case some time ago.

Actually VHDL is more synthesizable than Verilog

Re: VHDL or Verilog

It seems the big guys are droping support for VHDL. I remember the CEO of synposys announced their plan to phase out VHDL some times ago in a conference.

Re: VHDL or Verilog

Both are rudiments!!! They are redundanced and unjustified intricated. The idiea of combining simulation and synthesis languages in one - VHDL - is a permanent source of problems. At this day it's true - VHDL and Verilog are really work approach and they are very wide used. But evenly the best language for hardware synthesis is an Altera's AHDL. I hope not so long time for SystemC or AHDL-based non-vedor related language will be used.

For compare VHDL, Verilog and SystemVerilog look at this article:

Re: VHDL or Verilog

you can start by any one and after you become familiar with coding style using HDL programming you can easily migrate to the other side and can also decide which one is more suitable for your applications

If you are familiar with c programming, it is very easy to leaen HDL, but you must know hardware design well, otherwise you can't write good code for design.

Re: VHDL or Verilog

VHDL is strongly typed and better for learning/teaching strict/standard methodologies. Verilog is better for hacking together something quickly and getting erros during simulation time.

Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to