which is better to use RAM or FIFO

[Serwan Bamerni]

Dear all
I need to store a vector of data for more than 60 clock cycle and then use it.
i am confusing between which one to use for this case a RAM or a FIFO for optimum area and speed in my project, or if there is another better way for such case.

 

[FvM]

FPGA FIFO IP is based on block RAM and in so far using the same storage. You'll use a FIFO if you exactly need FIFO functionality, otherwise design the function you need with block RAM directly.

 

[shaiko]

"FIFO" (First In First Out) refers to the memory queuing mechanism - not the memory matrix itself. Therefore, it's possible to implement a FIFO using either RAM or Registers (Flip Flops) as the memory matrix.

With that said - registers are considered an "expensive" resource (compared to RAM). Therefore, if you don't need the functionality of a register - it'll probably be wiser to implement your FIFO's memory with RAM.

In your case, if all you need to do is store a single 60 bits wide vector - I don't see why you'd need a FIFO.

 

[Serwan Bamerni]

FPGA FIFO IP is based on block RAM and in so far using the same storage. You'll use a FIFO if you exactly need FIFO functionality, otherwise design the function you need with block RAM directly.

Do you mean that both FIFO and RAM take the same area and with same speed?

 

[Serwan Bamerni]

"FIFO" (First In First Out) refers to the memory queuing mechanism - not the memory matrix itself. Therefore, it's possible to implement a FIFO using either RAM or Registers (Flip Flops) as the memory matrix.

With that said - registers are considered an "expensive" resource (compared to RAM). Therefore, if you don't need the functionality of a register - it'll probably be wiser to implement your FIFO's memory with RAM.

In your case, if all you need to do is store a single 60 bits wide vector - I don't see why you'd need a FIFO.

That what I really mean
Does it is better to use register to implement FIFO or a RAM to do this function
As I understand from your answer that the RAM based is better.
by the way I need to store a vector of data for 60 clock cycle not a 60 bits wide vector

 

[FvM]

60 bits in total isn't much. It may be preferable to use registers.

The intersting question is what "then use it" exactly means. RAM content can be only accessed one address per clock cycle. So if you e.g. want to combine several bits in calculation, RAM won't work for it.

 

[ads-ee]

Lack of a good specification of what the OP wants has hindered answering their question.

Serwan, What is your bit width of the data you wish to delay for 60 clock cycles (which is what you seem to be asking how to do efficiently). Also you should state how many vectors of data are expected to arrive during a 60 clock cycle interval and will they be evenly spaced or randomly spaced.

RAM - you will have to generate addresses to read and write with a 60 clock delay. (think 60 deep circular queue)
FIFO - you will have to count clocks between starting the write and starting the reads. (think I need to count 60 clock cycles of delay)
SRL - you will be using the LUT memory as a shift register.
Shift register - wasteful of resources, unless you require access to multiple taps of the delayed data.

Regards

 

[Serwan Bamerni]

60 bits in total isn't much. It may be preferable to use registers.

The intersting question is what "then use it" exactly means. RAM content can be only accessed one address per clock cycle. So if you e.g. want to combine several bits in calculation, RAM won't work for it.

Thank you Mr. FvM for your help
My data is not 60 bits
It is a number of std_logic_vectors of 10 bits
and I want to delay each std_logic_vector for 60 clock cycle
and then I use each arrive std_logic_vector with other data prepared later

 

[shaiko]

It is a number of std_logic_vectors of 10 bits
and I want to delay each std_logic_vector for 60 clock cycle
and then I use each arrive std_logic_vector with other data prepared later

How many vectors?

 

[Serwan Bamerni]

Lack of a good specification of what the OP wants has hindered answering their question.

Serwan, What is your bit width of the data you wish to delay for 60 clock cycles (which is what you seem to be asking how to do efficiently). Also you should state how many vectors of data are expected to arrive during a 60 clock cycle interval and will they be evenly spaced or randomly spaced.

RAM - you will have to generate addresses to read and write with a 60 clock delay. (think 60 deep circular queue)
FIFO - you will have to count clocks between starting the write and starting the reads. (think I need to count 60 clock cycles of delay)
SRL - you will be using the LUT memory as a shift register.
Shift register - wasteful of resources, unless you require access to multiple taps of the delayed data.

Regards

Thank you Mr. ads-ee for your answer
the width of my std_logic_vector is 10 bit
the number of vector I want to store is also 60 vector which is then be used vector after vector.
form your description of different method of store data that FIFO is best suitable in my case. are that is right?

 

[Serwan Bamerni]

How many vectors?

60 vectors at each time
(i.e. when 1 vector is read another vector take its place

 

[shaiko]

In this case I'd use a FIFO that's based on RAM.
You can use the vendor's tool or write one yourself...

 

[ads-ee]

In this case I'd use a FIFO that's based on RAM.
You can use the vendor's tool or write one yourself...

My preference would be RAM not a FIFO. With the FIFO you will have control logic that you will be stuck with (unless you are using a Xilinx part with built in FIFO controllers), and then you still need external control logic to implement the 60 clock cycle delay (offsetting the start of the reads from the writes). With a RAM design you only need to have two counters offset by 60 addresses (which are reset to those values). Both counters are incremented on every clock cycle. Giving you a 60 clock cycle delay. The offset is directly controlled instead of hidden in combination of FIFO address generation and an external counter.

Or if you use distributed RAM (looking at Xilinx 6 input LUT) You can implement an SRL that is 60 deep using 20 LUTs (each lut can be a SRL32).