verilog versus vhdl
Recently, I worked in Europe for two large well known semiconductor companies. Both of whom were using Verilog 2001 and System Verilog.
Vhdl is used primarily for projects funded by the government and fits in with the designed by committee culture of such project rather than the verilog "nuts and bolts" approach. VHDL is also taught at a number of universities, probabably due to government funding of research. However, just about every company in the commerical sector uses verilog.
And don't kid yourselves...VHDL is COMPLETELY UNSUITABLE AS A SYSTEM MODELING LANGUAGE... You would have to be completely insane to throw away your copy of Matlab and C++ in favor of VHDL... On the other hand, Verilog doesn't pretend to be something its not... Instead, the philosophy of verilog is to make it easier to compile C++ together with verilog if system level models are needed.
that's why they are called "Hardware Description Languages"... VHDL and Verilog have only one goal... to describe and test hardware implementations... Personally, I would much rather write a testbench in Verilog than VHDL.. so in that sense, VHDL completely fails as a system language. Secondly, if I had to design a filter, or some other alogirthm, I'm not going to do that by coding HDL first! that would be completely ludicriuos! No, instead, i'm going to startup matlab or write some c-code. So let's stop pretending that VHDL is a system language... its not... nobody wants to model algorithms with a crippled ADA compiler that's been modified to model hardware implementations.. and thus you still need to use the proper tool for the job.... It exactly the same reason, that C++ makes a poor hardware description language... SystemC anybody?
If VHDL is a system language, then I hereby declare that everybody should stop programming in C++ and use only VHDL for everything!
thus we can have VHDL device drivers, VHDL GUI's, VHDL Operating Sytems... VHDL matlab... VHDL everywhere... give me a break...