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none of these.
Draw a table of possible states and input signals and you'll know the answer.
I presume the question refers to state before and after a clock edge and doesn't consider asynchronous inputs.
Yes, because a 0 or 1 level at input D forces a respective next output state, independent of present state.I think current option is 1(D flip flop.)
Yes, because a 0 or 1 level at input D forces a respective next output state, independent of present state.