Which DRC checks are done exclusively in ATPG step?

[ajukrishnan]

During the DFT insertion stage, we check for the DRC rules such as:

• Clocks are controlled
• Asynchronous set/reset are controlled
• Clock gating cells are enabled
• bidirectional pins are set to in/out during shift

etc..

But which are the DRC rules which are checked only in ATPG step and not in Scan insertion stage? Is the rule that "only one Tristate bus enable must be active" checked in Scan Insertion stage or in ATPG stage?
I went through the tool manual and found out S(scan chain) rules which are checked only in scan insertion. But other rules I cannot distinguish whether it is done only in Scan insertion or in ATPG.

 

[rca]

During the ATPG, first the DFT DRC are check, and after it looks at the netlist, atpg-clock not connected to clock and data pins of memory element...