T
treez
Guest
Hello,
Please assist on the best way to make a common mode choke for our SMPS output?
We are doing a common mode choke for the output of our 48V 6.7A output SMPS.
We want as little differential mode inductance as possible (as little leakage inductance as possible).
This is because output inductance will not help the stability situation.
Which Common mode choke in the attached will have the lowest leakage inductance? Can you estimate it in each case?
(a single three turn coil has a 10.75uH inductance)
The common mode choke is well needed because we have several SMPS’s in parallel, and without the chokes (at the output of each one) , there will be large ground loops in which noise currents can flow.
Torroid datasheet:
https://www.farnell.com/datasheets/...MI_NGs4dnd6AIVCLLtCh3CTADWEAAYASAAEgIWQfD_BwE
Please assist on the best way to make a common mode choke for our SMPS output?
We are doing a common mode choke for the output of our 48V 6.7A output SMPS.
We want as little differential mode inductance as possible (as little leakage inductance as possible).
This is because output inductance will not help the stability situation.
Which Common mode choke in the attached will have the lowest leakage inductance? Can you estimate it in each case?
(a single three turn coil has a 10.75uH inductance)
The common mode choke is well needed because we have several SMPS’s in parallel, and without the chokes (at the output of each one) , there will be large ground loops in which noise currents can flow.
Torroid datasheet:
https://www.farnell.com/datasheets/...MI_NGs4dnd6AIVCLLtCh3CTADWEAAYASAAEgIWQfD_BwE