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which common centriod pattern is better 4 differential pair?

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syiling

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differential pair spacing ratio

hi, i would like to have some advice on the floorplan of common-centriod layout for differential pair transistor. may i know which pattern is the best? or is there any alternatives besides those 3 patterns shown below? may i know too, whether 4 rows is better than 2 rows when we are doing the common centriod?

A= device +M1(multiplier=32), B=device -M1(multiplier=32), U=dummy transistor

pattern1:
U A A B B A A B B A A B B A A B B U
U B B A A B B A A B B A A B B A A U
U A A B B A A B B A A B B A A B B U
U B B A A B B A A B B A A B B A A U

pattern2:
U A A B B A A B B A A B B A A B B U U B B A A B B A A B B A A B B A A U
U A A B B A A B B A A B B A A B B U U B B A A B B A A B B A A B B A A U

pattern3 (almost same as pattern2 but without the dummy in the middle):
U A A B B A A B B A A B B A A B B B B A A B B A A B B A A B B A A U
U A A B B A A B B A A B B A A B B B B A A B B A A B B A A B B A A U


thank you for the advice.:D
 

erikl

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Re: which common centriod pattern is better 4 differential p

syiling said:
hi, i would like to have some advice on the floorplan of common-centroid layout for differential pair transistor. may i know which pattern is the best? or is there any alternatives besides those 3 patterns shown below? may i know too, whether 4 rows is better than 2 rows when we are doing the common centroid?
For getting lowest variation on such a block, you should select a block type with an aspect ratio as close as possible to 1 (i.e. to a quadratic form). This means, the w/l ratio of your transistors should decide upon using 2 or 4 rows.

If the decision is using 2 rows, I'd suggest a modified version of your pattern3:

U A A B B A A B B A A B B A A B B A A B B A A B B A A B B A A B B U
U B B A A B B A A B B A A B B A A B B A A B B A A B B A A B B A A U

For 32 units per transistor in total, you could also use groups of 4 (or even 8 ) A or B in series, which facilitates the routing. Try to keep the routing in good symmetry, too.
 

deepak242003

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four rows is better only if routing is too much critical.... due to increased complexity in routing ...

among the remaining two ,
i would prefer 1st one for <130nm
and 2 nd one for >130nm.. due to LOD efect coming into pic below 130 nm..
 

syiling

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Re: which common centriod pattern is better 4 differential p

hi deepak242003, thanks for the info sharing.

i would like to ask if the transistor length is much smaller than 45nm, does it mean it is better to use 4 rows (pattern 1) to achieve the common centriod? may i know the reason behind it?

thanks for the advice.:D

Added after 5 minutes:

hi erikl,

thanks for the advice. i would like to ask some further question as i am still new in drawing analog layout.
would you explain more on this statement "you should select a block type with an aspect ratio as close as possible to 1 (i.e. to a quadratic form). This means, the w/l ratio of your transistors should decide upon using 2 or 4 rows. "--- does it mean to use pattern1, i need to have w/l= 1? what would happen if the pattern1 is used for w/l=5? what would be your advice if the w/l=5?

may i know what is the acpect ratio close to 1 means?

thanks for the advice.:D
 

erikl

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Re: which common centroid pattern is better 4 differential p

syiling said:
hi erikl, ...
would you explain more on this statement "you should select a block type with an aspect ratio as close as possible to 1 (i.e. to a quadratic form). This means, the w/l ratio of your transistors should decide upon using 2 or 4 rows. "--- does it mean to use pattern1, i need to have w/l= 1?
Yes. With a w/l= 1 and 4 rows you'll come closer to a (nearly) quadratic block form.

syiling said:
what would happen if the pattern1 is used for w/l=5? what would be your advice if the w/l=5?
In this case - if you arrange the channels in vertical direction - a 4-rows-block would get
much higher than wide, a bad aspect ratio. So, in such case 2 rows should get closer to a quadratic block form.

syiling said:
may i know what is the acpect ratio close to 1 means?
Apart from random (statistical) variations, also process-induced linear variation gradients over the wafer area exist. As their angle dependency isn't known, a round or quadratic block area guarantees the highest probability for minimum parameter variation. See also the appended paper.
 

deepak242003

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Re: which common centriod pattern is better 4 differential p

syiling said:
hi deepak242003, thanks for the info sharing.

i would like to ask if the transistor length is much smaller than 45nm, does it mean it is better to use 4 rows (pattern 1) to achieve the common centriod? may i know the reason behind it?

thanks for the advice.
If you are drawing the layout below 90nm, you must first get familiar to well proximity and Lenght of Diffusion ( STI stress effect)..

you can download this paper from here :
www.ieee-cicc.org/06-8-6.pdf

In my previous post i meant to say matching.. by mistake i typed routing...
It depends on how critical the matching requirement is as the complexitiy of routing increases..

cheers...
 

syiling

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Re: which common centriod pattern is better 4 differential p

hi erikl,

when you mentioned about w/l=1, from the patterns shown in your suggestion (the modified pattern3), lets just said that the w/l for each transistor = 5/1;
with 2 rows, meaning the w=10 and there are 32 transistors in one row for both A & B devices. there fore the w/l=10/32 (2 rows with 32 transistor in each row)= 0.3.
the aspect ratio is not near to 1.

for second scenario, if using pattern1, there are 4 rows with 16 transistor in each rows. therefore the w= 5x4 and l=16 (if w=5, l=1), then the aspect ratio we get is 1.25.

for 2 scenarios shown above, it would be better if the differential pair is split into 4 rows for common centriod?

thanks for the advice.
:D
 

erikl

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Re: which common centriod pattern is better 4 differential p

syiling said:
... lets just said that the w/l for each transistor = 5/1;
with 2 rows, meaning the w=10 and there are 32 transistors in one row for both A & B devices. there fore the w/l=10/32 (2 rows with 32 transistor in each row)= 0.3.
the aspect ratio is not near to 1.
Yes, you're right; it's not good.

syiling said:
for second scenario, if using pattern1, there are 4 rows with 16 transistor in each rows. therefore the w= 5x4 and l=16 (if w=5, l=1), then the aspect ratio we get is 1.25.
Right. Considering the necessary S & D contacts, Design Rules for spacing, and routing space, you'll possibly get even closer to 1 .

syiling said:
for 2 scenarios shown above, it would be better if the differential pair is split into 4 rows for common centriod?
Yes! And it's named centroid, not centriod :D
 

kumarans

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Hai Guys,
I have one dout
which below mentioed pattern is good and avoid the gradient and offset voltage??????????

ABAB ABBA
BABA vs. BAAB
ABAB BAAB
BABA ABBA

Rgds
Kumaran.S
 

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