#### syiling

##### Newbie level 4

**differential pair spacing ratio**

hi, i would like to have some advice on the floorplan of common-centriod layout for differential pair transistor. may i know which pattern is the best? or is there any alternatives besides those 3 patterns shown below? may i know too, whether 4 rows is better than 2 rows when we are doing the common centriod?

A= device +M1(multiplier=32), B=device -M1(multiplier=32), U=dummy transistor

pattern1:

U A A B B A A B B A A B B A A B B U

U B B A A B B A A B B A A B B A A U

U A A B B A A B B A A B B A A B B U

U B B A A B B A A B B A A B B A A U

pattern2:

U A A B B A A B B A A B B A A B B U U B B A A B B A A B B A A B B A A U

U A A B B A A B B A A B B A A B B U U B B A A B B A A B B A A B B A A U

pattern3 (almost same as pattern2 but without the dummy in the middle):

U A A B B A A B B A A B B A A B B B B A A B B A A B B A A B B A A U

U A A B B A A B B A A B B A A B B B B A A B B A A B B A A B B A A U

thank you for the advice.