Whethe to add vdd!/gnd! in verilog file to generate layout by Encounter RTL-to-GDSII

[arvind_hatkar]

Hi all,

I have used UofU_TechLib_ami06 Technology
I have created verilog RTL Level design file fulladder_struct.v(given below) and written script syn-rtl.tcl
I have used UofU_Digital_v1_2 library, and UofU_Digital_v1_2.lef, UofU_Digital_v1_2.lib, UofU_Digital_v1_2.v

module fulladder (a, b, ci, s, co);
input a, b, ci;
output s, co;
assign {co,s}=a+b+ci;
endmodule

I have used Cadence Encounter(R) RTL Compiler-Version v09.10 to generate fulladder_RTL.v and fulladder_RTL.sdc,
fulladder_RTL.v and fulladder_RTL.sdc is given to Cadence Encounter(R) RTL-to-GDSII-Version v09.14 as an input.

I have used Cadence Encounter(R) RTL-to-GDSII-Version v09.14 to generate fulladder.def,fulladder.v and fulladder.sdf,
fulladder.v is imported in Virtuoso(CIW) to generate Schematic in Virtuoso Schematic Editor,
fulladder.def is imported in Virtuoso(CIW) to generate Abstract Layout in Virtuoso Layout Editor.

1) I have tried generating Layout using RTL Compiler then Encounter finally Virtuoso Layout Editor,
then tried for generating Schematic in Virtuoso Schematic Editor.
After this carried out DRC, Extractor, LVS, which is completed successfully, rules files used are divaDRC.rul, divaEXT.rul, divsLVS.rul respectively and Rules Library is UofU_TechLib_ami06.
Then done Simulation,found Simulation of Schematic is OK; showing correct results, but Post Layout Simulation is Not OK, i.e. found wrong simulation results.

2) Then I have created Layout from Schematic (which is generated by importing fulladder.v) Manually from Virtuoso Schematic Editor, Layout is similar as that of Layout generated by importing fulladder.def
Carried out LVS, found LVS successful;
Carried out Simulation of Schematic, found OK showing correct results,
Carried out Simulation of Post Layout Simulation, which is also found OK, showing correct results,

3) Than I rectified the problem, and found that there is no vdd! and gnd! Pin in the Layout generated by importing fulladder.def in Virtuoso(CIW) to generate Abstract Layout in Virtuoso Layout Editor.

4) Not only this but also I have confirmed the problem. I have removed the vdd! and gnd! pins from the layout which I have generated Manually (according to point 2), and carried out LVS, found LVS successful,
Then carried out Post Layout Simulation, found same wrong results (as in point 1).

My Questions are

Q1) How to add vdd! and gnd! Pin in layout generated by Encounter(R) RTL-to-GDSII ?
Q2) Whether to add vdd! and gnd! Port in fulladder_struct.v or in fulladder_RTL.v ?
Q3) Whether to add vdd! and gnd! Pin in Encounter(R) RTL-to-GDSII, if yes how and when to add ?

-I have tried adding Port vdd! and gnd! in fulladder_struct.v, but Encounter(R) RTL Compiler is giving errors.
-I have tried adding Port vdd! and gnd! in fulladder_RTL.v, but Encounter(R) RTL-to-GDSII is giving errors.
-I have tried adding PIN vdd! and gnd! in Virtuoso Layout, but Virtuoso Layout is giving errors.

Q2) As said in point 4, why LVS complited successfully even after removing vdd! and gnd! Pins from Layout?

Thanks to edaboard, for giving such platform to exchange our knowledge.

 

[rca]

The power pins will be added in the encounter tool at the floor plan step.

 

[arvind_hatkar]

I am a new user, as per my knowledge Floor-planning means Specify Floor-plan, in that there is no field/option for vdd! and gnd! Pins to add.
Will you please pin-point a particular step which I need to carry-out.
Also, if vdd! and gnd! Pins are not there in verilog file port listing, how Encounter will generate Layout consisting vdd! and gnd! Pins?

- - - Updated - - -

I am a new user, as per my knowledge Floor-planning means Specify Floor-plan, in that there is no field/option for vdd! and gnd! Pins to add.
Will you please pin-point a particular step which I need to carry-out.
Also, if vdd! and gnd! Pins are not there in verilog file port listing, how Encounter will generate Layout consisting vdd! and gnd! Pins?

 

[arvind_hatkar]

Found solution to my Problem vdd!/gnd!.
Now I can carry out Post Layout Simulation (Extracted View) of layout generated by Encounter and imported in Virtuoso Layout Editor.
Solution is
If you want the nets to be picked up in the extracted view (of Layout generated by Encounter and imported in Virtuoso Layout Editor) , and
called gnd!/vdd!, then you will have to place a gnd!/vdd! pin polygon at the top level on the appropriate bus(gnd!/vdd!) i.e. on Power Rings.
Thanks to all