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Next step is to create a Micro-architecture doc/spec. Some leads/pointers:
1. Are you designing Master or Slave or both? If it is for student project I recommend you do Slave RTL with master Testbench to keep it simple/started.
2. What testbnech language?
3. What tools do you have? If you have VCS or 0-in then you can leverage on provided AHB checkers in SVA/0-in for verification
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