Where to change the skew if it doesn't match after optimization?

[mujju433]

After doing optimization also if my skew doesn't meet then where will u go and change the skew???????????????

 

[shavakmm]

Re: skew

possible solutions:
1) may be skew constraint is too much tight.....try to reduce it !
2) u can try with usefull skew optimization

https://asic-soc.blogspot.com

 

[A.Anand Srinivasan]

Re: skew

then you would have to take to the solution of pipelining your circuitry.....

 

[pramodm]

skew

change your design archirechture

 

[kanagavel_docs]

Re: skew

Hi,

If you are working with ISE just check the clock is using Global clock buffer or ordinary buffer. If it uses ordinary buffer the clock will have large skew.

Regards,
Kanags

 

[mujju433]

skew

Wts this ISE?

 

[master_picengineer]

skew

Xilinks ISE (Integrated Software Envirement) is a software for Xilinks FPGA simulation, P&R & synthesis.

 

[denmos]

Re: skew

If you mean clock-skew, you can refer the answer in below.

Clock skew is difference from highest insertion delay and lowest insertion delay of clock tree.
You should build the clock-tree better to increasing clock-skew. Don't separate the clock tree if possible! Or you can search CTS distributtion from this forum for your details.

thanks!

 

[firewire2035]

skew

you can always manually adjust the skew.

 

[iwpia50s]

skew

By definition skew is the difference in insertion delay between any registers under a specified clock tree. If you are not meeting skew then your cts tool is crap and you will need to manually fix the skew by adding or deleting buffers. Either way it is not something you want to do manually.

 

[rajesh9999]

Re: skew

Possible solutions :

1. Increase insertion delay and run cts again
2. Start with a different clock tree topology (as the pervious topology might have had a local minima).

 

[sekapr]

Re: skew

if the skew is more and not fixable by cts then you need to change clock tree structure

 

[firewire2035]

skew

or may be you can use the skew to retime your datapath.

 

[xinsu]

skew

You should balance skew/insertion delay and clock buffer/inverter types in oder to get reasonable clock tree,and this will useful for later optdesign