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If you mean clock-skew, you can refer the answer in below.
Clock skew is difference from highest insertion delay and lowest insertion delay of clock tree.
You should build the clock-tree better to increasing clock-skew. Don't separate the clock tree if possible! Or you can search CTS distributtion from this forum for your details.
By definition skew is the difference in insertion delay between any registers under a specified clock tree. If you are not meeting skew then your cts tool is crap and you will need to manually fix the skew by adding or deleting buffers. Either way it is not something you want to do manually.