This makes no sense : ( SPDIF stream is usually continuous, as far as I'm aware. So, how would the buffer become empty?
Also, if you're dynamically changing the clock to your DAC as the buffer is getting empty, then this is a form of distortion.
Better to either just clock the DAC at the rate at which you're receiving the samples, since the SPDIF stream will have a
fairly accurate clock, or buffer a second or so, and not implement the variable DAC clock that you're considering. In the
unlikely event that the buffer becomes empty, then insert silence.
Are you sure you don't want to do silence insertion or something? That is very different.
You might want to simulate the scheme (Matlab or similar) before implementing.