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What are your requirements for the registers? You know that a RAM is controlled by an adress input (ot two independent adress inputs in case of a dual-port RAM). So you can only access one (or maximum two) regsisters at a time/a clock cycle. Is your register usage compatible with this restriction?
What are your requirements for the registers? You know that a RAM is controlled by an adress input (ot two independent adress inputs in case of a dual-port RAM). So you can only access one (or maximum two) regsisters at a time/a clock cycle. Is your register usage compatible with this restriction?
RAM usage for registers is particularly effective if the data is accessed sequentially or one-out-of-N registers has to be selected alternatively, e.g. for slow and medium speed filters, calibration tables etc.
For xilinx, you have three choices:
1.) registers only
2.) block ram
3.) distributed ram
distributed ram works well in the 16-128 item range (1 slice). for 100 16b registers, I'd use distributed ram. You can infer either using similar constructs, so you can decide to use BRAM or distributed ram later.
For xilinx, you have three choices:
1.) registers only
2.) block ram
3.) distributed ram
distributed ram works well in the 16-128 item range (1 slice). for 100 16b registers, I'd use distributed ram. You can infer either using similar constructs, so you can decide to use BRAM or distributed ram later.
Look at the SLICEM configuration. a depth of 16 is nice because it is a 4b address, so the addressing can be done in one slice. A depth of 16 or 32 allows a 6b/slice configuration. 128b lines up well with a 1b/slice option. Thus all of these options allow rams to be made without needing additional muxing logic. For narrow busses, deeper distributed rams may be ok as the extra muxing logic is still not that bad. As the bus width grows, BRAM becomes more attractive. As depth/width expands further, several BRAM are required an external RAM (DDR3) becomes attractive. On the lower end, 1-15 elements are also possible if needed, but use around the same amount of logic as a depth of 16.
For CPU applications, DMEM's ability to have a 3 read, 1 write structure can also be an advantage.
BRAM is useful and it functions like a stack..you can rewrite and use bram so therefore ur using a fixed number of resources of memory.you can point to a address location just like pointers and it helps you also in indexing the data values.
BRAM is useful and it functions like a stack..you can rewrite and use bram so therefore ur using a fixed number of resources of memory.you can point to a address location just like pointers and it helps you also in indexing the data values.
A BRAM is just a memory. A stack is a programming concept. You could create a stack and put it in BRAM if you wanted, but they are 2 completly different things.
i do agree its is not a COMPLETE stack...however u need just the address to get the data from the bram just like an pointer....and you can use it multiple times...
A pointer is another programming concept. At hardware level there are no pointers. Just raw addresses.
I dont understand what you mean by "you can use it miltiple times". With any memory you provide and address, you get data from that address or write data to that address. Thats all there is to it.
BRAM is useful and it functions like a stack..you can rewrite and use bram so therefore ur using a fixed number of resources of memory.you can point to a address location just like pointers and it helps you also in indexing the data values.
Uhm, no. A block ram is boring random access memory. You can use a bram to implement a stack, but bram is less limited (regarding access patterns) than a stack. Also, all mammals are cows! moooo!
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